Cleaning and liquid contact with solids – Processes – Hollow work – internal surface treatment
Reexamination Certificate
1999-07-09
2002-03-05
Gulakowski, Randy (Department: 1746)
Cleaning and liquid contact with solids
Processes
Hollow work, internal surface treatment
C134S001100, C134S011000, C134S022140, C134S030000, C134S026000, C216S067000, C216S074000, C216S078000, C438S905000
Reexamination Certificate
active
06352081
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of cleaning a semiconductor device processing chamber after the performance of a copper etch process in that chamber. In particular, the invention pertains to a multi-step dry cleaning method which results in the removal of nonvolatile etch byproducts from surfaces of the processing chamber after a copper etch process.
2. Brief Description of the Background Art
In the multilevel metallization architecture used in present day semiconductor devices, aluminum is generally used as the material of construction for interconnect lines and contacts. Although aluminum offers a number of advantages in ease of fabrication, as integrated circuit designers focus on transistor gate velocity and interconnect line transmission time, it becomes apparent that copper is the material of choice for the next generation of interconnect lines and contacts. In particular, when the aluminum wire size becomes smaller than 0.5 &mgr;m, the electromigration resistance and the stress migration resistance of aluminum becomes a problem area. In addition, when the feature size of an aluminum-based contact requires an aspect ratio of greater than 1:1, it is difficult to obtain planarization of the substrate during the application of the next insulating layer over the contact area of the substrate. Further, the resistivity of copper is about 1.4 &mgr;&OHgr;cm, which is only about half of the resistivity of aluminum.
There are two principal competing technologies under evaluation by material and process developers working to enable the use of copper. The first technology is known as damascene technology. In this technology, a typical process for producing a multilevel structure having feature sizes in the range of 0.5 micron (&mgr;m) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a diffusion barrier layer and, optionally, a wetting layer to line the openings; deposition of a copper layer onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using chemical-mechanical polishing (CMP) techniques. The damascene process is described in detail by C. Steinbruchel in “Patterning of copper for multilevel metallization: reactive ion etching and chemical-mechanical polishing”,
Applied Surface Science
91 (1995) 139-146.
The competing technology is one which involves the patterned etch of a copper layer. In this technology, a typical process would include deposition of a copper layer on a desired substrate (typically a dielectric material having a barrier layer on its surface); application of a patterned hard mask or photoresist over the copper layer; pattern etching of the copper layer using wet or dry etch techniques; and deposition of a dielectric material over the surface of the patterned copper layer, to provide isolation of conductive lines and contacts which comprise various integrated circuits. One advantage of the patterned etch process over the damascene process is that it is easier to etch fine patterns into the copper surface and then deposit an insulating layer over these patterns than it is to get the barrier layer materials and the copper to flow into small feature openings in the top of a patterned insulating film.
Methods for patterned etching of copper layers on the surface of semiconductor device substrates are disclosed, for example, in commonly owned, copending U.S. application Ser. Nos. 08/911,878 and 09/130,893, filed Aug. 13, 1997 and Aug. 7, 1998, respectively. Patterned etching of copper was performed in a plasma etch chamber including a decoupled plasma source (DPS) of the kind described by Yan Ye et al. at the Proceedings of the Eleventh International Symposium of Plasma Processing (May 7, 1996) and published in the
Electrochemical Society Proceedings
(Volume 96-12, pp. 222-233, 1996).
Unfortunately, patterned etching of copper is not a problem-free process. One potential productivity issue for copper etch in a high ion density (i.e., having an electron density of at least 10
11
e
−
/cm
3
) etch chamber is the heavy deposition of nonvolatile etch byproducts onto available surfaces inside the etch chamber. These byproducts typically include, among others, compounds of copper, such as copper chloride (CuCl
2
) and copper oxide (CuO), and compounds of silicon, such as silicon oxide (SiO
2
).
If the byproduct is allowed to build up to a certain thickness (i.e., more than a few microns) on upper surfaces of the chamber, the weight of the deposited byproduct can cause pieces of the byproduct to break off the chamber surface and fall onto the surface of a wafer being processed in the chamber, resulting in contamination of the wafer and low product yield. Often, only a small number of wafers can be processed before the byproduct deposition on surfaces of the chamber builds up to an unacceptable level. The chamber must therefore be cleaned frequently between wafer runs, increasing the chamber downtime and decreasing the wafer throughput.
Several patents and publications disclose cleaning procedures for the removal of etch byproducts and residues from various surfaces. U.S. Pat. No. 5,100,504, issued Mar. 31, 1992 to Kawai et al., discloses a method of cleaning a silicon surface. In the first step, a silicon oxide film is etched away using a CHF
3
gas, which etches the silicon oxide film in preference to the underlying silicon. After the silicon oxide film is removed, organic matter of the C
x
F
y
group remains on the silicon surface. In the second step, the organic matter is etched away using an NF
3
gas. The NF
3
gas easily formed F radicals which react with the organic matter to provide a residue-free silicon surface. At the time of forming this F radical, no residue which makes the silicon surface dirty is formed.
U.S. Pat. No. 5,356,478, issued Oct. 18, 1994 to Chen et al., discloses a plasma cleaning method for removing residues previously formed in a plasma treatment chamber by dry etching layers, such as photoresist and barrier layers, on a wafer. The method includes introducing a cleaning gas mixture of an oxidizing gas and a chlorine-containing gas into the chamber, followed by performing a plasma cleaning step. The plasma cleaning step is performed by activating the cleaning gas mixture and forming a plasma cleaning gas, contacting interior surfaces of the chamber with the plasma cleaning gas, and removing residues on the interior surfaces. The cleaning gas mixture can also include a fluorine-based gas. For instance, the cleaning gas can include Cl
2
and O
2
and, optionally, CF
4
. An advantage of the cleaning method is that it is not necessary to open the plasma treatment chamber.
U.S. Pat. No. 5,735,692, issued Apr. 7, 1998 to Hillman, discloses a silicon substrate cleaning method and apparatus in which a hydrous cleaning solution is caused to evaporate at a temperature at about or above its azeotropic temperature and a cleaning vapor produced in this manner is applied to a substrate to remove unwanted oxide thereon. This method can be applied to a series of silicon substrates with consistent results. The method is said to produce an oxide-free substrate without contaminants, particulates or residue.
U.S. Pat. No. 5,756,400, issued May 26, 1998 to Ye et al., discloses an apparatus and process for plasma cleaning the interior surfaces of semiconductor processing chambers. The method is directed to the dry etching of accumulated contaminant residues attached to the inner surfaces of the plasma processing chamber and includes the steps of introducing a cleaning gas mixture of a halogen-containing gas; activating a plasma in an environment substantially free of oxygen species; contacting the contaminant residues with the activated cleaning gas to volatilize the residues; and removing the gaseous byproducts from the chamber. The etchant gaseous mixture comprises at least one fluorine-containing gas and an equal or le
Hsieh Peter
Lu Danny Chien
Shih Hong
Xu Li
Ye Yan
Applied Materials Inc.
Church Shirley L.
Gulakowski Randy
LandOfFree
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