Method of changing the power dissipation across an array of tran

Details Method of changing the power dissipation across an array of tran Method of changing the power dissipation across an array of tran

1998-06-01

2000-10-31

Dutton, Brian

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438289, 257401, H01L 218234, H01L 21336, H01L 2976, H01L 2994, H01L 31062

Patent

active

061401846

ABSTRACT:
A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).

REFERENCES:
patent: 4918333 (1990-04-01), Anderson et al.
patent: 4924111 (1990-05-01), Anderson et al.
patent: 5003370 (1991-03-01), Kashiwagi
patent: 5365099 (1994-11-01), Phipps et al.
patent: 5895255 (1999-04-01), Tsuchiaki

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