Method of automating chip power consumption estimation...

Details Method of automating chip power consumption estimation... Method of automating chip power consumption estimation...

2005-03-08

2005-03-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06865722

ABSTRACT:
An apparatus, system and method of automatically computing power consumption estimation of a chip are provided. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generated power consumption values of the macros are stored, the power consumption value of each macro. After doing so, the power consumption value of the chip is automatically computed. The apparatus, system and method also compute a desired power consumption estimation of the chip as well as a plurality of power densities. A desired power consumption estimation is based on a desired voltage and a desired frequency while a power density is power used in a certain area. Further, the apparatus, system and method reproduces the floorplan of the chip and represents each area within the chip by a different color to illustrate hot spots and cool spots.

REFERENCES:
patent: 5754435 (1998-05-01), Sato
patent: 6321185 (2001-11-01), Takahashi
patent: 6338025 (2002-01-01), Bowen et al.
patent: 6367061 (2002-04-01), Kurokawa et al.
patent: 6598209 (2003-07-01), Sokolov

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