Method of automated design and checking for ESD robustness

Details Method of automated design and checking for ESD robustness Method of automated design and checking for ESD robustness

2000-10-04

2004-04-20

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06725439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit design, checking and verification and more particularly to methods of integrated circuit placement, wiring, checking and verification for electrostatic discharge robustness.
2. Background Description
Electrostatic discharge (ESD) protect devices, connected to integrated circuit (IC) chip's input/output (I/O) pads to protect circuits on the chip from ESD damage are well known in the art. ESD damage may result from ESD between any two chip pads. Typically, prior art ESD devices were designed and located based on well understood requirements of the particular circuit or, cell, and the physical characteristics of the chip technology and the ESD protect device. Thus, for a single power supply chip, the ESD device may have been, merely, a pair of reverse biased diodes, each connected between the supply or its return line (ground) and an IC chip signal pad.
The characteristics of (i.e., the level of protection afforded by) these prior art ESD protect devices were determined by the pad to ESD device wiring and the circuit attached to the pad. The design objective is to insure that the ESD device turns on before the circuit or wiring to the circuit fails. Thus, wiring between the pad and the ESD device must be wide enough to transfer the charge to the device without failing during the transfer.
However, even with a wire that is wide enough, if its resistance is too high, due to its length, the combination of the resistance and wiring/ESD device capacitance filters the charge provided to the ESD device, reducing its effectiveness. Under some circumstances, the wiring resistance in the I/O net wiring may act as a voltage divider. If the pad to device resistance is high enough, the voltage dropped across the divider resistance may prevent the device from ever turning on.
As long as what is typically referred to as the chip image (the template for an IC defining pad locations and chip size) is well defined, the above problems can be adequately addressed fairly simply by design. Thus, in
FIG. 1
which shows an example of a prior art standard chip image
50
, the chip has well defined circumferentially located I/O cells
52
and ESD protect devices (not shown) predefined power busses connected to an external connection pad
54
. Circumferentially located signal pads
56
are connected through the ESD protect devices to I/O cells
52
.
Typical electrical characteristics considered in designing an ESD network are: type of wiring metal (aluminum or copper, etc.), as well as wire and via (inter metal-metal layer connections) dimensions, i.e., widths, lengths, thicknesses and contact sizes. Thus, for a standard image
50
by design, each individual I/O cell may have a fixed, well defined internal resistance associated with it, thereby assuring the ratio of fixed wire resistance to internal cell resistance.
Advances in IC technology have increased circuit density, increasing the number of circuits on a single chip. The increase in the number of circuits has led to a corresponding increase in the number of pads for off chip connections, i.e., for chip inputs/outputs (I/Os) and for supplying power and ground to the chip according to what is well known in the art as Rent's Rule.
Consequently, to take full advantage of this increased IC chip gate count and complexity and to provide more locations for chip pad connections, standard chip images such as chip image
50
in
FIG. 1
cannot be used.
Further, ESD protection is more complex on a multiple supply chip. Besides providing a supply path and a ground or return discharge path, paths must be provided from each pad
54
to each additional power supply line and each additional return line. Each signal pad
56
must be connected through an ESD protect device to each supply and each return. An ESD device for such a typical multi-supply IC chip may be nothing more than a string of diodes. Other chip characteristics, such as a power sequencing requirement, may further complicate the device.
So, for example, on a 2-supply chip, even a circuit in an I/O cell
52
connected to a single supply still requires a an ESD protection path through a device connected between its connecting pad and the unused (by that I/O circuit) supply. While this requirement may be met without difficulty for a standard image chip
50
by including protect devices periodically spaced around the chip's perimeter; it makes wiring an already complex chip even more difficult for a non-standard image chip.
Further complicating this, is that with the increased I/O count requirement on state of the art non-standard image IC chips, I/O cell placement is not restricted to the chip's periphery, the normal location for ESD devices. Instead, with a non-standard area array footprint, wires connecting I/O circuits to the chip pads are routed individually, either automatically by a design system or, interactively by a designer. Further, power busses are not as well defined and do not provide the extra protection from the added capacitance found on prior art standard images
50
.
Thus, there is a need for integrated circuit chips with pad array interconnections having robust ESD protection and for a system and method for designing IC chips with robust ESD protection and verifying the IC chip design.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to improve integrated circuit chip ESD protection.
It is another purpose of the present invention to allow free form I/O cell placement on integrated circuit chip without impairing chip ESD protection.
It is yet another purpose of the present invention to verify ESD protection on integrated chips.
The present invention is a integrated circuit (IC) chip with ESD robustness and the system and method of designing and verifying the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a supply or ground line, either directly or through an ESD protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or return lines is inserted. Thus, wiring is such that wires and vias to ESD protect devices are wider than signal wires. All chip pads have adequate ESD protection. The I/O power bus has robust ESD protection.
The design may then be verified.


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