Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-23
2001-03-13
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S307000
Reexamination Certificate
active
06200864
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to high-denisity semiconductor devices, and in particular, to a method of asymmetrically doping a region beneath a gate by controlling the lateral surface doping profile of the gate.
BACKGROUND OF THE INVENTION
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source, and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide layer. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packaging density and reduce parasitic overlap capacitance between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to produce a gate that provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant, the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage, leakage current, breakdown voltage, and drive current of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate after sidewall spacers have been formed thereon. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however lightly doped regions are typically formed for both the source and the drain to avoid additional processing steps.
Disadvantages of LDDs include increased fabrication complexity and increased parasitic resistance due to their light doping levels. During operation, LDD parasitic resistance decreases drain current. Linear drain current (i.e., drain current in the linear or triode region) is reduced by the parasitic resistance in both the source and the drain. Saturation drain current (i.e., drain current in the saturation region) is largely unaffected by the parasitic resistance of the drain but greatly reduced by the parasitic resistance of the source. Therefore, saturation drain current can be improved while reducing hot carrier effects by providing a lightly doped region only on the drain side. That is, the drain includes lightly and heavily doped regions, and the entire source is heavily doped.
Asymmetrical IGFETs (with asymmetrically doped sources and drains) are known in the art. For instance, U.S. Pat. No. 5,286,664 entitled “Method For Fabricating The LDD-MOSFET” by Horiuchi describes forining a gate, implanting lightly doped source and drain regions using the gate as an implant mask, forming a photoresist layer that covers the source side and exposes the drain side, depositing a single spacer on the drain side using liquid phase deposition (LPD) of silicon dioxide, stripping the photoresist, and inplanting heavily doped source and drain regions using the gate and single spacer as an implant mask.
A drawback to these and other conventional asymmetrical IGFETs is that the heavily doped source and drain regions typically have identical dopant concentrations. Although the doping concentration of the heavily doped drain region may be constrained in order to reduce hot carrier effects, the doping concentration of the heavily doped source region need not be constrained in this manner. Furthermore, increasing the doping concentration of the heavily doped source region reduces the source-drain series resistance, thereby improving drive current. U.S. Pat. No. 5,789,787, entitled “Asymmetrical N-Channel And P-Channel Devices” describes a method directed at overcoming some of these disadvantages, and is relatively complex in operation.
Accordingly, a need exists for an improved method of producing an asymmetrical doping profile without the drawbacks described above.
SUMMARY OF THE INVENTION
The present invention advantageously provides a method of asymmetrically doping a region beneath a gate. The present invention achieves this result by controlling the lateral surface profile of the gate using a mask.
The present invention advantageously provides a first embodiment of a method of asymmetrically doping a region beneath a gate that includes forming a mask over the gate such that it extends beyond the opposing sides of the gate in an uneven manner. The present invention relies upon lateral diffusion during the implantation of a well to modulate the doping profile of the channel region. By modifying the positioning of the mask above the gate (i.e., the amount the mask extends beyond the opposing side of the gate), it is possible to define an asymmetric lateral channel profile, which can be advantageously used to vary gate overlap, channel V
T
, or source/drain doping as necessary. The ion implantation produces well regions on both sides of the gate that overlap within the channel region directly beneath the gate. The uneven manner in which the mask is positioned above the gate results in more dopant being present on a side of the channel region that has less mask extending beyond that side of the gate, than dopant on an opposing side of the channel region.
The present invention advantageously provides a second embodiment of a method of asymmetrically doping a region beneath a gate that includes forming sidewall spacers on both sides of the gate in an uneven manner. An exemplary embodiment includes the formation of two sidewall spacers on a side of the gate and a single sidewall spacer on an opposing side of the gate, where the two spacers extend a distance from the gate that is greater than a distance the single spacer extends from the gate. A second exemplary embodiment includes the formation of a single sidewall spacer on both sides of the gate, where the spacers extend from the gate by unequal distances. The second embodiment uses sidewall spacers formed on both sides of the gate in an uneven manner to define an asymmet
Advanced Micro Devices , Inc.
Pham Long
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