Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-09-13
2004-06-15
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S117000, C438S122000, C438S124000, C438S126000, C438S127000
Reexamination Certificate
active
06750082
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to packaging integrated circuits.
BACKGROUND OF THE INVENTION
Packaged integrated circuit (IC) having plastic, epoxy or resin packages encapsulating the die (semiconductor chip) and a portion of the lead frame and leads are produced using a variety of methods.
U.S. Pat. No. 5,891,377 to Libres et al. describes lead frames, mold chases and mold flashes in a dambarless leadframe process.
U.S. Pat. No. 4,615,857 to Baird describes an encapsulating method for reducing flash.
U.S. Pat. No. 6,309,916 B1 to Crowley et al. describes a method of molding a plastic body of a semiconductor package.
U.S. Pat. No. 5,949,132 to Libres et al. describes a method and apparatus for encapsulating an integrated circuit die and leadframe assembly using dambarless leadframes.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a improved method of assembling an integrated circuit package with an exposed die back.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.
REFERENCES:
patent: 4615857 (1986-10-01), Baird
patent: 5155068 (1992-10-01), Tada
patent: 5891377 (1999-04-01), Libres et al.
patent: 5949132 (1999-09-01), Libres et al.
patent: 6117797 (2000-09-01), Hembree
patent: 6184062 (2001-02-01), Brofman et al.
patent: 6188127 (2001-02-01), Senba et al.
patent: 6309916 (2001-10-01), Crowley et al.
patent: 6548330 (2003-04-01), Murayama et al.
patent: 2001-144218 (2003-05-01), None
Wolf et al, “Silicon Processing for the VLSI Era, vol. 2—Process Integration”, 1990, Lattice Press, pp. 66-67.
Briar John
Hwee Tan Kim
Perez Roman
Ackerman Stephen B.
Advanpack Solutions Pte. Ltd.
Picardat Kevin M.
Saile George O.
Stanton Stephen G.
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