Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-03-08
2011-03-08
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S110000, C716S118000, C716S119000, C716S123000
Reexamination Certificate
active
07904869
ABSTRACT:
A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.
REFERENCES:
patent: 5309371 (1994-05-01), Shikata et al.
patent: 5481472 (1996-01-01), Chung et al.
patent: 6067409 (2000-05-01), Scepanovic et al.
patent: 6099580 (2000-08-01), Boyle et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6407434 (2002-06-01), Rostoker et al.
patent: 6442743 (2002-08-01), Sarrafzadeh et al.
patent: 6961916 (2005-11-01), Sarrafzadeh et al.
patent: 6961936 (2005-11-01), Bhatti
patent: 7126837 (2006-10-01), Banachowicz et al.
patent: 7155693 (2006-12-01), Rodman
patent: 7277309 (2007-10-01), Banachowicz et al.
patent: 7308667 (2007-12-01), Katagiri
patent: 2004/0037474 (2004-02-01), Happel
patent: 2006/0041851 (2006-02-01), Gallatin et al.
patent: 2006/0112355 (2006-05-01), Pileggi et al.
U.S. Appl. No. 11/423,240, filed Jun. 9, 2006.
U.S. Appl. No. 11/366,286, filed Mar. 2, 2006.
Hector Scott D.
Maziasz Robert L.
Stanley Claudia A.
Vasck James E.
Yu Kathleen C.
Balconi-Lamica Michael J.
Doan Nghia M
Freescale Semiconductor Inc.
Vo Kim-Marie
LandOfFree
Method of area compaction for integrated circuit layout design does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of area compaction for integrated circuit layout design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of area compaction for integrated circuit layout design will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2725755