Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-19
2004-03-09
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000, C710S100000
Reexamination Certificate
active
06704896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and a device for getting information output on an internal bus in order to facilitate the detection of a malfunction position in a memory or the like stored in a microcomputer.
2. Description of the Prior Art
Recently, because of the increasing size of programs, processes growing in sophistication, and so on, improvements in performance are required of microcomputers. Speeding up the clock is effective for improvements in performance and is actually used as a means for improving the performance of microcomputers. In general, speeding up the clock is done for the CPU, first. This results in reducing “the minimum instruction execution time”, which is used as an indicator showing the performance of microcomputers.
Next to speeding up the clock for the CPU, improvements in the speed of memories stored in microcomputers are done in order to improve the performance of microcomputers. Microcomputers include types with or without stored memories. The type of microcomputer without a stored memory that receives instructions directly from outside is not adapted to facilitate memory speedup. The type of microcomputer with a memory stored therein that supplies instructions read out of the memory to the CPU is adapted to increase the memory speed and hence improve the performance of the microcomputer. The present invention is associated with a microcomputer with a memory stored therein. The term “memory” designates a memory stored in the microcomputer. A mask ROM, EPROM, EEPROM, or a SRAM is frequently used as a memory stored in the microcomputer. Increases in memory speed are required due to the need for speeding up a means for supplying instructions to the CPU, which arises as the CPU speed is increased. Even when the CPU can operate at a high clock speed, the CPU may idle if the speed of the memory used for supplying instructions to the CPU is low as compared with the CPU speed.
In general, speeding up the memory is more difficult than speeding up the logic of the CPU or the like. As the amount of memory is increased, the degree of difficulty in speeding up the memory is increased. In other words, there is a trade-off between speeding up the memory and increasing the amount of memory. This results in difficulty in designing the memory. In most cases, there is no margin in the timing design of the memory. Furthermore, in order to make the memory satisfy design specifications, transistors with a very large current driving capability are frequently used to constitute the memory. As a result, the power consumption is increased and the risk of malfunctions due to noise is increased.
As previously mentioned, the memory is a component that must be designed to strict specifications during the design of the whole microcomputer, and has the highest risk of not operating as designed when tested after the chip is manufactured. When the memory does not operate as designed, the need for detection of a malfunction position in the memory arises. In order to detect a malfunction position in the built-in memory, there is a need to monitor input/output signals to or from the built-in memory in order to determine if each input/output signal has a desired value.
Because data transfer between the memory and the CPU is carried out by way of an internal bus stored in the microcomputer, the data transfer between the memory and the CPU cannot be monitored directly from outside the chip. A problem with the prior art is therefore the costs in time and effort associated with identifying that part of a user program in which the memory malfunctions.
While it is possible to facilitate an analysis of the built-in memory using a tool such as an in-circuit emulator or ICE, much time and effort are needed and a high degree of reliability cannot be ensured because such a tool uses an indirect method of estimating data to be output by the built-in memory from resultant outputs by the execution of the user program.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above problems. It is therefore an object of the present invention to provide a method of and a device for getting information output on an internal bus in order to facilitate reliable and speedy detection of a malfunction position in a built-in storage element, such as a memory stored in a microcomputer, while reducing expenses in time and effort for the analysis of the storage element stored in the microcomputer.
In accordance with one aspect of the present invention, there is provided a method of getting information output onto an internal bus to facilitate detection of a malfunction position in a storage element stored in a microcomputer during execution of a user program, the method comprising the steps of: setting a target address specifying a memory access that is expected to cause the built-in storage element to malfunction to a register, by executing an interruption handling program; latching and holding information output onto the internal bus in respose to a match between an address output onto the internal bus and the target address set to the register; and reading the latched and held information.
Preferably, the method further comprises the step of, in response to a match between an address output onto the internal bus and the target address set to the register, stopping the execution of the user program by generating an interruption signal.
In accordance with another aspect of the present invention, there is provided a method of getting information output onto an internal bus to facilitate detection of a malfunction position in a storage element stored in a microcomputer during execution of a user program, the method comprising the steps of: setting a maximum count value to a down counter after the expiration of a predetermined time interval after starting the execution of the user program and then causing the down counter to start decreasing its count value one by one at every clock cycle at the same time that the maximum count value is set to the down counter, the maximum count value corresponding to a number of clock cycles that elapses during execution of a predetermined part of the user program that is to be checked in order to identify a malfunction position in the built-in storage element; latching and holding information output onto the internal bus once the down counter underflows; reading the latched and held information to compare the information with its desired value and then determine whether the built-in storage element malfunctioned within a time period during which the down counter was decreasing its count value; restarting the execution of the user program while delaying the timing of setting the maximum count value to the down counter during the execution of the user program until identifying a part of the user program in which the built-in storage element malfunctions; and reducing the current maximum count value set to the down counter by half in order to narrow the identified part of the user program in which the built-in storage element malfunctions down to a first or second half of the identified part, and further determining whether the built-in storage element malfunctions in the first or second half.
In accordance with a further aspect of the present invention, there is provided a device for getting information output onto an internal bus to facilitate detection of a malfunction position in a storage element stored in a microcomputer during execution of a user program, the device comprising: a down counter to which a maximum count value is set, the maximum count value corresponding to a number of clock cycles that elapses during execution of a part of the user program that is to be checked in order to identify a malfunction position in the built-in storage element, and the down counter starting at the same time that the maximum count value is set, decreasing its count value one by one at every clock cycle, and generating an underflow signal when it underflows; and a latch unit for latching and holding inf
Burns Doane , Swecker, Mathis LLP
Lamarre Guy J.
Mitsubishi Denki & Kabushiki Kaisha
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