Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-11-24
2002-03-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C370S224000, C714S738000
Reexamination Certificate
active
06353908
ABSTRACT:
TECHNICAL FIELD
The invention relates to a method of, and a circuit arrangement for, digitally transferring bit sequences in selective manner between a higher-order circuit part and a lower-order circuit part. Taking over English language usage, one often speaks of master and slave in conjunction with higher-order and lower-order circuit parts. The term host also is commonly employed for the higher-order circuit part. In practical embodiments, the master circuit part may be a microcontroller and the slave circuit part may be a function block having function means such as control means and measuring means.
BACKGROUND OF THE INVENTION
The master circuit part and the slave circuit part usually cooperate via a bus system by means of which digital signals can be transferred between the master circuit part and the slave circuit part. The signal transfer via the bus system is subject to a defined protocol, which is frequently referred to as bus protocol.
A known bus system is the so-called SPI (Serial Peripheral Interface) with the associated SPI bus protocol. This is shown, for example, in the data sheet of the company Aureal Semiconductor, relating to circuit VSP 901, pages 12 and 13, dating from February 1997.
The signal representation shown in
FIG. 7
of said publication is depicted herein in attached FIG.
13
. In this figure:
SCK is the serial clock
HREQ is the host request signal
SS is the slave select signal
MOSI is the Master Out Slave In (transfer from master to slave)
MISO is the Master In Slave Out (transfer from slave, to master)
SPICMD is an additional signal that extends the SPI protocol to indicate whether the master has placed a register address or register data on the SPI bus.
Some operating features of the SPI bus protocol will now be discussed briefly by way of FIG.
13
.
Signal HREQ has a logic value L (LOW) when the master is ready to receive a 24-bit data word. The slave is connected to the master via a slave select line SS. Via these slave select lines, the host informs the slave when it intends to send the particular data information to the slave. The respective data word is transferred via the MOSI lines from the host or master to the slave, and a data word transmitted before is transferred back to the master or host via the MISO line. Upon occurrence of the first clock pulse of the next data word to be transferred, HREQ is set to logic value H (HIGH) by the master. The master scans SPICMD and sets HREQ to H when it is ready to receive the next data word. If SPICMD is L, this indicates the transfer of a register address. If SPICMD is H, this indicates the transfer of a register value. The host deactivates the SS line after it has written the last bit to the master. In case the host deactivates the SS line of the receiving master before the end of the data word transfer since the host has to settle first a task of higher priority, the data word transfer is aborted and the master discards the received data.
FIG. 12
shows in a block circuit diagram a circuit arrangement suitable for the SPI protocol, comprising a master circuit part e.g., in the form of a microcontroller &mgr;C, a serial interface SI and a slave circuit part in the form of a multi-function block MFB accommodating e.g., six functions F
1
to F
6
. The functions F
1
to F
6
in total require, for example, a data field having a data field width or data bit number of 30. A data bus DB connecting the serial interface SI and the multi-function block MFB thus has a corresponding data field width of 30 bits. The microcontroller &mgr;C and the serial interface SI are connected to each other via three terminals: a serial input Sin, via which serial bit sequences can be transferred from microcontroller &mgr;C to serial interface SI, a serial output Sout, via which serial bit sequences can be transferred from serial interface SI to microcontroller &mgr;C, and a clock terminal CLK, via which a system clock can be supplied to serial interface SI.
In a data transfer, the data for all functions F
1
to F
6
must be transferred each time. Thus, a data transfer with a data width of 30 bits is necessary each time. When a function needs to be reprogrammed, writing over of all functions FB
1
to FB
6
is necessary. This involves the risk that functions whose programming actually is to remain unchanged are erroneously programmed in a different manner.
The SPI protocol involves some problems.
1. When during transfer from master to slave a data value is corrupted, the corrupted or falsified data value is written to the target register of the slave, without the master being informed of whether a correct or an incorrect data transfer has taken place.
2. When a data value is corrupted within a slave, the master is not notified thereof. To overcome this problem, an examination (which is not provided for in the SPI protocol) of the entire reading back operation and a new write operation would have to be carried out. This would consume operating time of the master and delay the entire data transfer.
3. The SPI protocol uses a fixed data word length. Each bit within this fixed data word length has a specific function. When one of the master or slave is altered with respect to one or parts of its functions, all functions have to be programmed anew, also the functions that are not to be altered. This means that also the functions not requiring new programming have to be written over. This increases the risk of erroneous programming changes.
4. In case one or several functions are to be added later on, this necessitates as a rule a hardware change. The interface between master and slave is designed for the fixedly determined data word length, which in the example shown in
FIG. 12
is a data word length of 30 bits. If, by adding additional functions, an increase in the data word length becomes necessary, both the interface and the process control will have to be changed.
The present invention has the object of overcoming such problems. In particular, more flexibility with respect to functional changes and extensions of functions as well as increased safety as regards a correct data transfer are to be achieved.
SUMMARY OF THE INVENTION
The invention to this end makes available a method and a circuit arrangement, which can be developed in advantageous manner in accordance with the description herein. In addition thereto, a test bit generator is provided, which is of significance both for the method and for the circuit arrangement.
The method provides a bus protocol for digitally transferring bit sequences in selective manner between a master means and several selectively controllable slave means via an interface means provided therebetween, making use of bit sequences of predetermined maximum frame length, comprising an address field addressing the respective slave means to be controlled, a control field containing control information, and a data field. While the address field and the control field each have a predetermined field length or bit number, the data field for the slave means may have different field lengths or data bit numbers as long as the data field does not exceed a (freely selectable) maximum data bit number. The bit sequences transferred in serial form are written in succession to successive register stages of an interface register and read back to the master means. Reading back is carried out register stage for register stage immediately after having been written to the respective register stage where writing to a register stage and reading back from this register stage take place during the same clock pulse. The master means compares the bit read-back from the respective register stage with the bit transmitted for this register stage. When the read-back memory contents of any of the register stages are not in conformity with the bit transmitted from the master means for this register stage, the master means blocks the transfer of the respective transmitted bit sequence to the respective addressed slave means.
This method ensures that a bit read incorrectly to the interface register is immediately recognized
De'cady Albert
Jorgenson Lisa
Lamarre Guy
SEED IP Law Group PLLC
STMicroelectronics GmbH
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