Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-26
2005-07-26
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C438S219000, C438S284000
Reexamination Certificate
active
06921688
ABSTRACT:
A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked. After the LOCOS isolation technique has been fully implemented, the flash area is then preferably masked and the STI technique is implemented in order to define the SRAM area of the silicon substrate on which the SRAM cell is implemented. After the STI technique is implemented, the flash EPROM and the SRAM cells are preferably formed. Thus, the SRAM cells and the flash EPROM cells are both implemented on the common silicon substrate, but yet are appropriately isolated from each other, as well as from other additional devices which may be further implemented on the same silicon substrate, while providing the advantages of respective isolation schemes for the two cells.
REFERENCES:
patent: 4658283 (1987-04-01), Koyama
patent: 4892614 (1990-01-01), Chapman et al.
patent: 5169792 (1992-12-01), Katoh et al.
patent: 5200636 (1993-04-01), Uemura et al.
patent: 5498566 (1996-03-01), Lee
patent: 5559348 (1996-09-01), Watabe et al.
patent: 5605853 (1997-02-01), Yoo et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5702988 (1997-12-01), Liang
patent: 5723895 (1998-03-01), Takahashi
patent: 5833745 (1998-11-01), Atsuki et al.
patent: 5898619 (1999-04-01), Chang et al.
patent: 5930619 (1999-07-01), Noble
patent: 6051868 (2000-04-01), Watanabe et al.
patent: 6060348 (2000-05-01), Yang et al.
patent: 6124882 (2000-09-01), Voois et al.
patent: 6128240 (2000-10-01), Cutter et al.
patent: 6133640 (2000-10-01), Leedy
patent: 6136652 (2000-10-01), Hazani
patent: 6141242 (2000-10-01), Hsu et al.
patent: 6141706 (2000-10-01), Thornton et al.
patent: 6141739 (2000-10-01), Provence et al.
patent: 6153476 (2000-11-01), Inaba et al.
Alliance Semiconductor
Ha Nathan W.
Haverstock & Owens LLP
Pham Long
LandOfFree
Method of and apparatus for integrating flash EPROM and SRAM... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of and apparatus for integrating flash EPROM and SRAM..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of and apparatus for integrating flash EPROM and SRAM... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3422563