Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-23
2002-07-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S302000
Reexamination Certificate
active
06426262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of analyzing the effects of shadowing of halo implants performed on a transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases “short-channel” effects. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched “off.” This is a result of, at least in part, the source/drain depletion regions being closer together because of the shorter channel length. Short-channel effects also include “threshold voltage roll-off” (i.e., the threshold voltage (V
th
) decreases as gate length is reduced), and the like.
In general, short-channel effects may be reduced by using angled halo implants. Angled halo implants are implants of dopants that effectively “reinforce” the doping type of the substrate in the channel between the source/drain extension regions (formerly known as lightly doped drain or LDD regions). For example, for an NMOS transistor, the doping type of the substrate in the channel between the N-type source/drain extension regions is a P-type dopant, e.g., boron (B) or boron difluoride (BF
2
). In this illustrative example, the halo implant process involves the use of P-type dopants implanted into the substrate at an angle (with respect to a direction horizontal to the surface of the substrate), and with a dose that may range from about 1.0×10
12
to 1.0×10
14
ions/cm
2
at an implant energy ranging from about 5-15 keV for boron and about 20-70 keV for boron difluoride.
Similarly, for a PMOS transistor, the doping type of the substrate in the channel between the P-type source/drain extension regions is an N-type dopant, e.g., arsenic or phosphorous. For example, an angled halo implant comprised of arsenic (As) may be implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0×10
12
to 1.0×10
14
ions/cm
2
at an implant energy ranging from about 40-70 keV for arsenic.
As shown in
FIG. 1
, for example, an illustrative field effect transistor
10
may be formed above a surface
15
of a semiconducting substrate
12
, such as doped-silicon. The substrate
12
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate electrode
14
formed above a gate insulation layer
16
that is formed above the surface
15
of the semiconducting substrate
12
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by dielectric sidewall spacers
20
. The sidewall spacers
20
may be formed above shallow source/drain extension regions
24
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices such as other transistors (not shown).
A typical prior art process flow to produce the structure depicted in
FIG. 1
will now be described. Initially, the trench isolations
18
are formed in the substrate
12
. Thereafter, the gate insulation layer
16
and the gate electrode
14
are formed by forming the appropriate layers of material above the substrate
12
, and thereafter patterning those layers by performing one or more etching processes to define the gate electrode
14
and the gate insulation layer
16
. A masking layer
29
, comprised of, for example, photoresist, is then formed above the substrate
12
and patterned to define an opening
21
, thereby exposing the gate electrode
14
and the gate insulation layer
16
. Next, halo implant regions
26
are formed. In particular, a halo implant process
25
is initially performed on one side of the device. Upon completion, the device may be rotated 180° and the halo implant process
25
may then be repeated to form a halo implant region
26
on the opposite side. In practice, the device
10
may be subjected to four halo implants during processing. Four implants are typically performed because many of the transistors formed above a substrate are oriented approximately 90° relative to one another.
Thereafter, a source/drain extension implant process (not shown) is performed to form the source/drain extension regions
24
. Note that the implant process is typically self-aligned with respect to the gate electrode, although some small amount of scattering may occur. Thereafter, sidewall spacers
20
are formed adjacent the gate electrode
14
. Then, a source/drain implant (not shown) is performed to form the doped region
28
. This source/drain implant is generally aligned with respect to the sidewall spacers
20
. Lastly, one or more anneal processes are performed to activate the implanted dopant atoms and to repair damage to the lattice structure of the substrate
12
. During these anneal processes, the implanted dopant materials migrate, or diffuse, from their implanted location in a more or less isotropic fashion. The post-anneal positions of the various doped regions are depicted approximately in FIG.
1
.
As shown in the illustrative NMOS device depicted in
FIG. 1
, P−-doped regions
26
resulting from angled halo implants are typically provided adjacent the N-doped source/drain extension regions
24
to reduce some of the short-channel effects described above. In particular, by “reinforcing” the P-doping type of the semiconducting substrate
12
in the channel between the N-doped source/drain extension regions
24
, the laterally non-uniform P−-doped angled halo implant regions
26
may improve the threshold roll-off (i.e., the threshold voltage (V
th
) decreasing as gate length is reduced), thereby reducing short-channel induced effects such as a non-zero drain-source leakage current when the transistor is supposed to be switched “off,” (i.e., “off-state” leakage).
The angle
27
of the halo dopant implant
25
with respect to a line parallel to the surface
15
of the semiconducting substrate
12
may normally lie within a range of about 30°-60°. Typically, the semiconducting substrate
12
is tilted at the angle
27
with respect to a horizontal direction in an implanter (not shown) and the halo dopant is directed downward in a vertical direction. Alternatively, the semiconducting substrate
12
could be disposed in the horizontal direction in the implanter (not shown) and the halo dopant implant could be directed downward at the angle
27
with respect to the horizontal direction in the implanter, and/or any other combination of tilt and implant direction could be used as long as the angle
27
is
Cheek Jon D.
Fuselier Mark Brandon
Wright Marilyn I.
Le Dung A
Nelms David
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