Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-12
2002-09-10
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06449751
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing integrated circuits for potential fabrication faults. More specifically, the present invention relates to a method of analyzing potential test vectors for use in static current testing of integrated circuits.
BACKGROUND OF THE INVENTION
Static current testing has been used to detect potential fabrication faults in complementary metal-oxide semiconductor (CMOS) circuits. Static current testing is based on an assumption that a fault-free CMOS circuit draws very little supply current in a steady state. This current is know as “leakage” current. Certain manufacturing faults on an integrated circuit cause unwanted shorts within the devices fabricated on the integrated circuit. Under certain test conditions, these shorts can cause an increase in the current drawn by the integrated circuit. A faulty integrated circuit often draws current that is several orders of magnitude greater than that drawn by a non-faulty integrated circuit.
Therefore, the leakage current drawn by an integrated circuit under certain test conditions can be used to indicated the presence of a manufacturing defect in the circuit.
Static current testing is performed by applying test vectors to the integrated circuit and making multiple current measurements during a quiescent state of the circuit. A test vector is typically applied to the circuit by serially shifting the test vector into the circuit through a chain of “scannable” elements and then clocking the circuit. The test vectors that are used for static current testing must contain vectors that will put the circuit into a low drain current (I
DD
) state. Static current testing is often referred to as I
DDQ
testing.
Once the circuit is in the desired state, the circuit is “strobed” near the end of a clock cycle. That is, a snap shot of the circuit is taken, and the status of selected pins and nets is recorded along with the stability of the circuit. The strobe point for each I
DDQ
test vector is usually the last time unit in the clock cycle. If the state of the circuit at a particular strobe point is such that a defect-free chip in that state would not draw supply current, then the test vector and the resulting test patterns obtained at that strobe point can be successfully used for I
DDQ
testing.
When selecting which test vectors can be used for static current testing of an integrated circuit, the response of the circuit to the potential test vectors is simulated on a functional model of the integrated circuit. Each test vector is scanned into the functional model, the model is then “clocked” and the resulting states on all pins, nets, etc. within the model are recorded at multiple instants in time. The recorded states are output in the form of a value change dump (VCD) file. The states in the VCD file are then analyzed to determine whether the particular vector is a candidate for I
DDQ
testing. An I
DDQ
analyzer checks the states of the circuit against a set of rules to determine whether the circuit would draw current in that state. If not, the vector producing that state is a potential test vector for the I
DDQ
test.
Due to the number of logic cells and nets in a typical integrated circuit, the VCD file sizes can become huge. One factor that contributes to the large file sizes is that all pins, nets, etc. are dumped for each test vector. With 100,000 gates or more being integrated on a single circuit, the number of recorded states can be in the millions. Also, the same physical net may be known by different logical names in the logical description of the circuit. For example, several different logical nets can be connected together to form a single physical net. If the states on each logical net in the netlist are recorded, the resulting VCD file will have a large number of redundantly recorded states.
The large VCD file sizes impair design turn-around time and reduce overall productivity in selecting test vectors. Thus, an improved method of analyzing potential static current test vectors, which produces reduced VCD file sizes, is desired.
SUMMARY OF THE INVENTION
One aspect of the present invention relates to a method of analyzing test vectors for use in measuring static current consumed by an integrated circuit. According to the method, a netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes.
Cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. A list of the nodes in the netlist that correspond to the identified pins is then generated. A computer software simulation program simulates a response of a functional model of the integrated circuit to a potential test vector and outputs logic states of the nodes in the list when the functional model is in a substantially steady state.
Another aspect of the present invention relates to a computer-aided design tool for analyzing static current test vectors for use in measuring static current consumed by an integrated circuit. The tool reads a netlist of interconnected cells to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. The tool also reads cell characteristics for selected ones of the cell types from a technology library to identify pins of the selected cell types to be monitored and then generates a list of the nodes in the netlist that correspond to the identified pins. Once the list has been generated, the tool simulates a response of a functional model of the integrated circuit to a potential test vector and outputs logic states of the nodes in the list when the functional model is in a substantially steady state.
Another aspect of the present invention relates to a computer readable medium having instructions readable by a programmable computer which, when executed, cause the computer to perform steps including: (a) reading a netlist of interconnected cells to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes; (b) for selected ones of the cell types, reading a technology library to identify any pins of the selected cell types that are listed as having a required logic state to place that cell type in a static power condition; and (c) generating an output computer file which lists the nodes in the netlist that correspond to the pins identified in step (b) and excludes at least some of the other pins of the selected cell types.
Yet another aspect of the present invention relates to a method of analyzing test vectors for use in measuring static current consumed by an integrated circuit. The method includes: (a) reading a netlist of interconnected cells to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes; (b) identifying pins of selected ones of the cell types to be monitored; (c) for each pin identified in step (b), (c)(1) identifying a net name for a net coupled to that pin in the netlist, (c)(2) locating any top net name within the netlist that is coupled to the net, (c)(3) adding the top net name to an output list if the top net name is located in step (c)(2), and (c)(4) adding the net name identified in step (c)(1) to the output list if no top net name is located in step (c)(2); (d) simulating a response of a functional model of the integrated circuit to a potential test vector with a computer software simulation program; and (e) outputting logic states from the simulation program when the functional model is in a substantially steady state for the net names that are listed in the output list.
REFERENCES:
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6378123 (2002-04-01), Dupenloup
Ghosh Pradipta
Gunda Arun K.
Hussain Hunaid
LSI Logic Corporation
Phan Trong
Westman Champlin & Kelly
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