Method in the manufacturing of a semiconductor device

Details Method in the manufacturing of a semiconductor device Method in the manufacturing of a semiconductor device

2000-03-21

2001-12-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S309000, C438S202000, C438S205000, C438S207000

Reexamination Certificate

active

06333216

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method of etching selectively when manufacturing semiconductor devices and to a method of manufacturing bipolar transistors while applying the selective etching method.
DESCRIPTION OF THE PRIOR ART
The trend in the design and manufacture of integrated circuits leans towards progressively smaller individual components of progressively higher performances. For instance, the dimensions of bipolar transistors are becoming progressively smaller, both horizontally and vertically, so as to increase packing densities and transistor speeds. Manufacturing precision has therewith become progressively more important, both with regard to individual process stages and with regard to the alignment between different layers.
There is normally used at present in the manufacture of bipolar high frequency transistors a technique that employs a self-registered base-emitter structure (T. H. Ning et al, “Self-Aligned npn Bipolar Transistors”, IEDM Techn. Dig., pages 823-824, 1980), which enables the transistor cell to be made smaller while obtaining a reduced base-collector capacitance and a reduced base resistance when the extrinsic base is connected to the intrinsic base in the immediate proximity of the emitter. Several variants of this method are known to the art.
U.S. Pat. No. 5,266,504 describes a method of manufacturing a self-registered bipolar transistor in which the base is grown epitaxially and the emitter is formed by the deposition of an amorphous silicon layer followed by a polycrystalline silicon layer, whereafter the structure is patterned and etched. The amorphous silicon layer is then recrystallized by SPE (Solid Phase Epitaxy). This method is able to provide a thin base and a sharp and well-controlled emitter-base junction.
U.S. Pat. No. 4,988,632 teaches the deposition of a polycrystalline silicon layer or an amorphous silicon layer on a substrate and doping of the layer. A layer of LTO (Low Temperature Oxide) or some other dielectric is deposited on said silicon layer, whereafter the structure is patterned and etched to provide a base electrode and emitter opening. U.S. Pat. No. 5,213,989 teaches a method of depositing a polycrystalline silicon layer, an amorphous silicon layer or some similar silicon-based layer on a substrate and doping said layer, whereafter a dielectric layer, preferably a TEOS-based (Tetra Ethyl Ortho Silicate-based) oxide is deposited over the silicon layer. The structure is patterned and etched in a known manner. It is not evident from U.S. Pat. Nos. 4,988,632 and 5,213,989 that the silicon layers shall be amorphous when etching out the emitter openings.
Those problems that occur when selectively etching away a polycrystalline silicon layer from a silicon substrate involve difficulties in stopping the etching process so that the polycrystalline silicon layer is removed completely without penetrating the substrate too deeply. The polycrystalline silicon layer is also etched at different speeds along different crystal directions and at grain boundaries, resulting in etching residues, so-called pillars, or in irregularities in the etched surface, so-called facets, and in blunt or dull edges in the etched openings. When the polycrystalline layer is to be doped by ion implantation, there is a risk of channelization of the dopant in grain boundaries or along crystal directions, meaning that the degree of doping cannot be controlled. Particularly when etching out the emitter opening in the manufacture of bipolar transistors that have a self-registered base-emitter structure, it is of the greatest importance that the aforesaid problems are overcome, since when the substrate is etched too deeply there is a risk of obtaining an excessively high series resistance or no electrical contact at all between intrinsic and extrinsic base. When doping to achieve a given type of doping, n or p, to form the emitter, there is also the risk of forming so-called pipes, i.e. channels of said doping type transversely through the intrinsic base, resulting in emitter leakage. These pipes are formed generally as a result of etching residues, so-called pillars.
SUMMARY OF THE INVENTION
The object of the present invention is to resolve the aforesaid problems and thus produce semiconductor components, particularly bipolar transistors, of higher quality and/or higher performance and/or of smaller size than those semiconductor components produced by hitherto known methods.
To this end, the inventive method includes the etching of amorphous silicon. Such silicon lacks crystal structures. The use of amorphous silicon thus removes many of the problems and drawbacks encountered when etching polycrystalline silicon.
The inventive method involves depositing an amorphous silicon layer on a crystalline silicon substrate. According to the invention, there is deposited on the amorphous silicon layer a protective dielectric layer such as to prevent crystallization of the amorphous layer. The dielectric layer is preferably deposited by one of the following methods: PECVD (Plasma Enhanced Chemical Vapor Deposition), SACVD (Sub Atmospheric Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy) or with the aid of a spin-on technique: The dielectric layer is preferably comprised of PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate). The resultant structure is patterned, whereafter the dielectric layer and the amorphous silicon layer are etched, for instance dry-etched, within a predetermined area.
The inventive etching method provides structures which have sharply defined edges and smooth pronounced etched surfaces in the absence of pillar or facet formation tendencies. Good etching selectivity between amorphous and crystalline silicon is also obtained. This results in semiconductor components of improved performance in relation to earlier semiconductor components. Particularly when fabricating a bipolar transistor having a self-registered base-emitter structure, the aforesaid etching process can be applied when etching-away the emitter opening in a manner which enables semiconductor devices of very small dimensions (length scales in the sub-micrometer range) to be produced. The advantages afforded by the present method include good etching selectivity when etching amorphous silicon on crystalline silicon, good CD control (Critical Dimension control), i.e. good control of the dimensions of the etched opening, and the avoidance of the risk of channelization of the dopant in the case of ion implantation processes.


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International Search Report for International Application No. PCT/SE96/01511.

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