Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-29
2005-11-29
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C716S030000
Reexamination Certificate
active
06971055
ABSTRACT:
A method for verifying the accuracy of bit-map memory test programs is disclosed, which employs a Focused Ion Beam (FIB) apparatus to make or break connections on one or more word lines or bit lines of the memory to be tested, causing abnormal data output from memory locations affected by such word lines or bit lines during FIB modeling. If abnormal data are also produced on the same electrical address corresponding to the physical memory address during the bit-map memory testing, that means the bit-mapping memory test program has passed the verification test, and it can be used to test other physical memory to check for any faulty address lines or memory cells; otherwise, the test program needs to be tuned through repeated correction process until the electrical addresses output from the test program match with the test pattern memory addresses.
REFERENCES:
patent: 6775796 (2004-08-01), Finkler et al.
patent: 6782499 (2004-08-01), Osada et al.
patent: 2003/0046621 (2003-03-01), Finkler et al.
patent: 2003/0177424 (2003-09-01), Ninomiya et al.
Hung Wen-Jyh
Wang Chien-Chiang
Jiang Chyun IP Office
Tu Christine T.
Winbond Electronics Corp.
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