Method for verifying hold time in integrated circuit design

Details Method for verifying hold time in integrated circuit design Method for verifying hold time in integrated circuit design

1997-05-05

2000-02-08

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

713401, 713503, G06F 104

Patent

active

060237678

ABSTRACT:
A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.

REFERENCES:
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5726596 (1998-03-01), Perez
patent: 5761097 (1998-06-01), Palermo
patent: 5812708 (1998-09-01), Rao

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