Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2005-03-01
2005-03-01
Thomas, Tom (Department: 2815)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S113000, C257S341000, C257S401000, C257S620000
Reexamination Certificate
active
06861337
ABSTRACT:
A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or “programmed” by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad mask are required for each new device. Wafers may also be manufactured and stored at an inventory location prior to contact or metal mask, significantly reducing the time required to manufacture new devices. It is also be possible to qualify a family of devices made using this approach without qualifying each device. In addition, the location of the source or the source and gate bonding pads may be easily moved for assembly in a new package or for a new application.
REFERENCES:
patent: 3753289 (1973-08-01), Berner
patent: 4086375 (1978-04-01), LaChapelle et al.
patent: 4902636 (1990-02-01), Akiyama et al.
patent: 4942447 (1990-07-01), Park et al.
patent: 5217916 (1993-06-01), Anderson et al.
patent: 5656843 (1997-08-01), Goodyear et al.
patent: 5872377 (1999-02-01), Jeon
patent: 6005271 (1999-12-01), Hshieh
patent: 6259497 (2001-07-01), McDonnell et al.
patent: 6603173 (2003-08-01), Okabe et al.
patent: 20020175353 (2002-11-01), Dray et al.
patent: 20030139020 (2003-07-01), Estacio
patent: 20030183860 (2003-10-01), Uchiyama et al.
David Mavis et al., “A Reconfigurable, Nonvolatile, Radiation Hardened Field Programmable Gate Array (FPGA) for Space Applications,” 10pp. www.APLDCon98/Papers/b8_mavis.pdf.
Charles W. Stirk et al., “Manufacturing Cost Analysis of Integrated Photonic Packages,” Bosonics Inc., 1472 North St., Boulder, CO 80304, presented Jan. 22, 1999, 10pp. www.spie.org/web/meetings/programs/pw99/confs/3631B.html.
“The Do's and Don'ts of Using MOS-Gated Transistors” 7pp. www.eetkorea.com/ARTICLES/2000MAY/2000MAY04_BD_BT_AN.PDF.
Diaz José R.
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
Thomas Tom
LandOfFree
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