Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-03-22
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S780000
Reexamination Certificate
active
06372545
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of fabricating microelectronic devices and specifically to methods of fabricating solder bumps on microelectronic devices.
BACKGROUND OF THE INVENTION
Under bump metal (UBM) deposition is proceeded by sputtering and electroplating, and the patterning is achieved by various wet etching techniques before the bump formation. The complexity in so forming the bump metal is the weakness of this process. For copper bump formation, it is not easy to find a suitable etcher for copper. Further, there are many wet-etching solutions for UBM such as NH
4
OH+CuSO
4
for copper etching and HF solution for titanium etching. Costs are increased due to the amount of wet-etching.
U.S. Pat. No. 5,767,010 to Mis et al describes a lift-off process for removing the solder dam.
U.S. Pat. No. 5,933,752 to Yanagida describes a process to form an undercoating by a lift-off process.
U.S. Pat. No. 5,866,475 to Yanagida describes a lift-off process for a barrier metal layer.
U.S. Pat. No. 5,888,892 to Yanagida describes a lift-off process in a bump process.
U.S. Pat. No. 6,077,765 to Naya describes a bump process with UBM steps.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a simpler method of under bump metal deposition/patterning.
Another object of the present invention is to provide a reduced cost method for under bump metal deposition/patterning.
A further object of the present invention is to provide a method for under bump metal deposition/patterning that reduces costs by eliminating wet-etching.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure is provided having an exposed I/O pad. A patterned passivation layer is formed over the semiconductor structure, the patterned passivation layer having an opening exposing a first portion of the I/O pad. A dry film resistor (DFR) layer is laminated, exposed and developed to form a patterned dry film resistor (DFR) layer over the patterned passivation layer. The patterned dry film resistor (DFR) layer having an opening exposing a second portion of the I/O pad. The patterned dry film resistor (DFR) layer opening having opposing side walls with a predetermined profile with an undercut. A metal layer is formed over the patterned dry film resistor (DFR) layer, the exposed third portion of the I/O pad, and over at least a portion of the opposing side walls of the patterned dry film resistor (DFR) layer opening. The patterned dry film resistor (DFR) layer is lifted off, along with the metal layer over patterned dry film resistor (DFR) layer and over at least the portion of the opposing side walls, leaving the metal layer over the exposed second portion of the I/O pad. The metal layer over the exposed second portion of the I/O pad being an under bump metal.
REFERENCES:
patent: 5767106 (1998-06-01), Mis et al.
patent: 5866475 (1999-02-01), Yanagida
patent: 5888892 (1999-03-01), Yanagida
patent: 5933752 (1999-08-01), Yanagida
patent: 6015652 (2000-01-01), Ahiquist et al.
patent: 6077765 (2000-06-01), Naya
patent: 6103552 (2000-08-01), Lin
patent: 6232147 (2001-05-01), Matsuki et al.
Chen Yen-Ming
Chu Cheng-Yu
Fan Fu-Jier
Fan Yang-Tung
Lin Kuo-Wei
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Stanton Stephen G.
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