Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2005-06-28
2005-06-28
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C365S189080, C365S189110, C365S191000, C365S206000, C365S204000
Reexamination Certificate
active
06912165
ABSTRACT:
Disclosed is a method and structure that controls an output driver by generating an output data path clock signal from a system clock signal and timing the programmable impedance of the output driver according to the output data path clock signal. The method/structure controls the timing of the line driver circuits according to the output data path clock signal. By timing the programmable impedance according to the output data path clock signal, the timing of delivery of an impedance control signal is coordinated with the timing of delivery of data. The method/structure also performs impedance updates on the output driver more frequently during initialization cycles than in cycles that occur after the initialization cycles expire using at least two differently timed clock dividers and a counter.
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Corson Phillip L.
Pilo Harold
International Business Machines - Corporation
McGinn & Gibb PLLC
Walsh, Esq. Robert A.
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