Method for translating physical cell-coordinates of a memory...

Details Method for translating physical cell-coordinates of a memory... Method for translating physical cell-coordinates of a memory...

2005-08-02

2005-08-02

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C711S202000, C711S206000

Reexamination Certificate

active

06925589

ABSTRACT:
A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the repeatable units, preparing a look up table for translating buffer coordinates of a reference unit of the repeatable units and displacing information from the look up table to correspond to the repeatable units.

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