Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-30
2001-03-06
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000
Reexamination Certificate
active
06197633
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates in general to the field of semiconductors, and specifically to a method for ensuring that the capacitance of a storage capacitor does not decrease when the integration level is increased, and even more specifically to a method for producing a memory cell with a storage capacitor having an electrode surface area that is greater than the surface area of the individual memory cell.
A memory cell having a storage capacitor with an electrode designed virtually as a planar plate and being configured parallel to a main surface area of the memory configuration is disclosed in Müller, “Bauelemente der Halbleiterelektronik”, [Components of semiconductor electronics], Springer, 4th edition, 1991, 256 ff. The capacitance of a storage capacitor is a function of the capacitor area and would ordinarily become smaller with an increased integration level and the associated reduction in size of the memory configuration. To address this problem, the abovementioned document proposes the design of a storage capacitor as a trench capacitor that is configured like a pot in a main area of a memory configuration. The latter discussed design for realizing a storage capacitor has a considerably greater outlay than the former discussed design for a storage capacitor.
A further possibility for maintaining a specific capacitor area with an increased integration level is shown in U.S. Pat. No. 5,290,726. This document describes a design of the storage capacitor as a fin stacked capacitor which is configured over the selection transistor of the memory cell. In this design, a first electrode of the storage capacitor has a cross-section with a plurality of fingers lying next to one another and above one another, in order to increase the electrode surface area and hence the capacitor area in comparison with a plate-like design of the first electrode. This design of the storage capacitor requires a certain minimum area above the selection transistor within which the capacitor can be formed. As the integration level increases, it is difficult to provide this minimum area which is necessary for forming the capacitor. Furthermore, the capacitor structure described requires a very complicated production method.
European Patent Application EP 06 57 935 A2 discloses a semiconductor memory configuration and a method for the production of the semiconductor memory configuration. The memory configuration includes storage capacitors that have first electrodes designed as electrode plates that are configured at a distance one above the other as well as parallel to an upper main surface area of the semiconductor memory configuration. Each respective electrode plate is electrically connected to a respective selection transistor of a memory cell by a contact plug. In accordance with
FIG. 3B
of that document, the individual contact plugs are designed with different lengths corresponding to the distance to the respective electrode plate.
Japanese Patent Application JP 03-153074 A and Japanese Patent Application JP 62-179759 A describe semiconductor memory configurations having storage capacitors which have electrodes in plate form.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a method for the production of an integrated semiconductor memory configuration that provides a sufficiently large capacitor area and/or a sufficiently large value of capacitance in a simple manner when the integration level is increased.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing an integrated semiconductor memory configuration having storage capacitors, which comprises:
providing a semiconductor body having a main surface with contacts and a memory configuration with a plurality of memory cells, each one of the memory cells having a selection transistor electrically connected to a respective one of the contacts;
depositing a plurality of alternating layers of an insulating material and an electrode plate onto the semiconductor body, the alternating layers disposed one above the other;
providing each one of the electrode plates with a lug projecting in a direction of a respective one of the contacts;
etching holes extending through the plurality of alternating layers of an insulating material and an electrode plate;
etching a plurality of holes through the plurality of alternating layers down to the main surface of the semiconductor body, each respective one of the holes being etched over a respective one of the contacts;
forming a plurality of contact plugs by filling the plurality of holes with conductive material, each contact plug being formed to electrically connect the lug of a respective electrode plate to a respective one of the contacts, and each of the contact plugs being formed with an upper end;
depositing an insulating layer on the upper ends of the plurality of contact plugs;
etching a trench extending through the plurality of alternating layers and being substantially perpendicular to the main surface of the semiconductor body;
isotropically etching away part of the insulating material of the plurality of alternating layers while leaving the plurality of contact plugs surrounded by the insulating material and allowing the electrode plates to project into the trench;
conformally depositing a dielectric layer on the electrode plates; and
filling the trench with at least one electrically conductive material to form a second electrode.
In accordance with an added feature of the invention, a material selected from the group consisting of noble metals and oxides is provided on sides of each electrode plate that face the dielectric layer; and a material selected from the group consisting of a high-&egr; material and a ferroelectric material is provided as the dielectric layer.
In accordance with a concomitant feature of the invention, before the trench filling step is performed, a thin layer of a material selected from the group consisting of noble metals and oxides is conformally deposited over the dielectric layer.
In this production method, first all of the electrode layers and the insulating layers therebetween are deposited. Then, the holes for the contact plugs are etched over the respective contacts and filled with conductive material. In this case, all of the contact plugs would have the same length and would be laterally electrically connected to protruding lugs of the electrode plates. Only one respective contact plug makes electrical contact with one respective electrode plate. This is possible because the lugs on the different electrode plates are laterally offset with respect to one another. In order to avoid a short circuit with the counter-electrode, in other words the second electrode, of the storage capacitors, another insulating layer must be deposited on the upper ends of the contact plugs in order to cover the ends of the contact plugs.
The invention provides a simplified process as compared to the prior art because etching of all of the contact holes can be performed at the same time, thereby requiring only one etching step for all of the contact holes.
In a further inventive feature of the method, a high-&egr; material or a ferroelectric material can be used as the dielectric layer. The electrodes, at least on their sides facing the dielectric, must have a noble metal, for example Pt, Ru, Ir, Pd, or oxides such as, for example IrO
2
, RuO
2
, LaSrCoOx or the like, or must consist completely of these materials. To form the counter-electrode, it is appropriate to first deposit one of the abovementioned materials conformally as a thin layer over the dielectric and then to fill the remaining trench with a further, electrically conductive material, for example polysilicon.
In the integrated semiconductor configuration produced in this way, the first electrodes of a group of memory cells are each designed as electrode plates and are located at a distance one above the other as well as parallel to a main surface area of the semic
Hartner Walter
Mazure-Espejo Carlos
Schindler Gunther
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
Tsai Jey
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