Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-28
2000-12-26
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438234, 438236, H01L 21336, H01L 218249
Patent
active
061658480
ABSTRACT:
The invention relates to a method for the production of a MOS-controlled power semiconductor component (30), which power semiconductor component (30) comprises, in a common substrate (31), a plurality of component cells which are arranged next to one another and are connected in parallel. A bipolar transistor formed by a collector region (33) of a first conductivity type, a superior base region (32) of a second conductivity type and an emitter region (37) of the first conductivity type, which emitter region is incorporated from above into the base region (32), is present in each component cell (59). A MOS channel structure (39, 42, 43) for controlling the bipolar transistor is provided on the emitter side, which MOS channel structure (39, 42, 43) comprises a source region (43) of the second conductivity type, which source region lies above the emitter region (37), a channel region (42) of the first conductivity type, which channel region as arranged on the edge side of the emitter region (37) between the source region (43) and the base region (32), and a gate electrode (39) which is arranged in an insulated manner above the channel region (42). Simple setting of the current density in the event of a short circuit and of the hole bypass resistance without additional process complexity is achieved by virtue of the fact that the channel width of the MOS channel structure (39, 42, 43) is structured and the structuring of the channel width of the MOS channel structure (39, 42, 43) is effected indirectly by means of one of the other mask steps used in the production process of the component.
REFERENCES:
patent: 4639754 (1987-01-01), Wheatley, Jr. et al.
patent: 4851888 (1989-07-01), Ueno
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5354421 (1994-10-01), Tatsumi et al.
patent: 5451798 (1995-09-01), Tsuda et al.
patent: 5538908 (1996-07-01), Kim
Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, p. 323, No Month 1990.
Asea Brown Boveri AG
Booth Richard
Lindsay, Jr. Walter
LandOfFree
Method for the production of a MOS-controlled power semiconducto does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for the production of a MOS-controlled power semiconducto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the production of a MOS-controlled power semiconducto will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-994031