Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2004-08-30
2009-08-25
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000, C257SE21690
Reexamination Certificate
active
07579239
ABSTRACT:
The present invention relates to a method for processing of a non-volatile memory cell (50) which comprises a double gate stack and a single access gate. The method combines a way of processing an access gate with drain implant, separate from source implant, in a self-aligned manner. The method of the present invention does not require mask alignment sensitivity and makes it possible to implant self-aligned an extended drain for erasing of the memory device. Furthermore, the method provides a way of performing separately drain and source implant with different doping without the use of an additional mask.
REFERENCES:
patent: 6091104 (2000-07-01), Chen
patent: 6133098 (2000-10-01), Ogura et al.
patent: 2002/0137290 (2002-09-01), Wils et al.
patent: WO 00/51188 (2000-08-01), None
patent: WO 03/015151 (2003-02-01), None
patent: WO 03/015172 (2003-02-01), None
Chaudhari Chandra
NXP B.V.
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