Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-16
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S306000
Reexamination Certificate
active
06391697
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for the formation of a gate electrode with a uniform thickness in the semiconductor device through the use of a difference in polishing selection ratio between a polymer and an oxide film.
DESCRIPTION OF THE PRIOR ART
There are shown in
FIGS. 1A
to
1
E sectional views setting forth a conventional gate formation method using a damascene process.
The structure shown in
FIG. 1A
is obtained by steps of depositing a pad oxide film
11
followed by a polysilicon film
12
on a semiconductor substrate
10
; selectively etching the polysilicon film
12
and the pad oxide film
11
to pattern the polysilicon film
12
for acting as a dummy pattern; depositing an insulating film such as a nitride film or an oxide film on top of the patterned polysilicon film
12
; etching the whole surface obtained so as to form an insulating film spacer
13
at a sidewall of the patterned polysilicon film
12
; depositing an insulating oxide film
14
for planarization on the polysilicon film
12
and the insulating film spacer
13
; and heat-treating the insulating oxide film
14
.
FIG. 1B
is a sectional view showing a structure obtained by applying a chemical-mechanical polishing (CMP) process to the insulating oxide film
14
using a slurry for oxide film until the patterned polysilicon film
12
is exposed. If the chemical-mechanical polishing is applied to the insulating oxide film
14
using a typical oxide film slurry having a very small polishing selection ratio between the polysilicon film
12
and the insulating oxide film
14
, when the patterned polysilicon film
12
is exposed, a chemical-mechanical polishing unevenness depending on a wafer region is induced, resulting in a position dependent thickness of the patterned polysilicon film
12
.
Then, the polysilicon film
12
and the pad oxide film
11
are removed. As a result, the insulating film spacer
13
is exposed at its side wall and an opening
100
with a wafer-region-dependent depth is formed as shown in FIG.
1
C.
FIG. 1D
is a sectional view showing that a gate oxide film
15
, a barrier metal film
16
and a tungsten film
17
are sequentially buried within the opening
100
, after which the chemical-mechanical polishing process is applied to the tungsten film
17
until the insulating oxide film
14
is exposed. The unevenness of the chemical-mechanical polishing causes the thickness of the tungsten film
17
buried within the opening
100
to be variable.
FIG. 1E
is a sectional view showing a structure obtained by etching a portion of the tungsten film
17
in the opening; depositing a mask nitride film
18
on the remaining tungsten film; and forming the gate electrode by polishing the mask nitride film
18
until the insulating oxide film
14
is exposed.
As shown in
FIG. 1E
, the elevation of the tungsten film
17
making the gate electrode is dependent upon the wafer region because while performing the chemical-mechanical polishing process on the insulating oxide film
14
using a typical slurry for oxide film polishing, with the polysilicon film
12
buried within the opening, an uneven polishing is applied to the polysilicon film
12
, resulting in the removal of the polysilicon film
12
but allowing the tungsten film
17
buried within the opening to have an uneven thickness along the wafer region.
As a result, the conventional damascene gate formation method discussed above suffers from a drawback in that the elevation of the gate is dependent upon the wafer region, rendering electrical properties of the gate unstable.
To overcome the foregoing problem, a method is proposed in which the thickness of the insulating film spacer and the oxide film is increased, but this method creates unnecessary burden to increase thickness of the spacer and film to be polished.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a method for the formation of a gate electrode with a uniform thickness in the semiconductor device through the use of a difference in polishing selection ratio between a polymer and an oxide film.
In accordance with a preferred embodiment of the present invention, there is provided a method for the formation of a gate electrode of a semiconductor device, comprising steps of depositing a polymer layer on a semiconductor substrate; selectively etching the polymer layer to form a patterned polymer; forming an insulating oxide film for planarization on a structure obtained at the above step; applying a chemical-mechanical polishing (CMP) process to the insulating oxide film, wherein the patterned polymer is used as a polishing stop layer; removing the patterned polymer to define an opening with its bottom defined by an exposed portion of the semiconductor substrate; forming a gate insulating film on the exposed semiconductor substrate within the opening; depositing an electrically conducting film on a structure obtained at the above step to bury the opening; applying the CMP process to the electrically conducting film to allow the electrically conducting film to remain only within the opening, wherein the insulating oxide film is used as a polishing stop layer; removing a portion of the electrically conducting film formed within the opening by etching; depositing a mask nitride film on a structure obtained at the above step to bury the top of the electrically conducting film; and applying the CMP process to the mask nitride film until the insulating oxide film is exposed.
REFERENCES:
patent: 6033963 (2000-03-01), Huang et al.
Hyundai Electronics Industries Co,. Ltd.
Le Dung A
Nelms David
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