Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-27
2003-04-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06557146
ABSTRACT:
BACKGROUND OF THE INVENTION
This application is based on and hereby claims priority to German Patent Application No. 198 14 109.2 filed on Mar. 30, 1998, the contents of which are hereby incorporated by reference.
The invention is directed to a method for comparing electrical circuits to one another.
In the design of a digital circuit, the quality assurance before the start of production requires 30% to 70% of the entire development time. During the quality assurance, attempts to find faults in the circuit are made by intensive simulation. Even after the end of the simulation, only a part of the behavior of a digital circuit has been investigated, so that it must always be considered that faulty designs can go into production. An inconsistency in an electrical circuit noticed after the beginning of production and a correction following thereupon require time-consuming and expensive refitting work.
The quality assurance is intended to assure that description forms of different phase of the circuit design for a circuit exhibit identical input/output behavior. It is thereby customary to represent (digital) circuits as finite automatons with Boolean input/output and truth values. Prof. Dr. Hans-Jochen Schneider (Editor), “Lexikon der Informatik und Datenverarbeitung”, R. Oldenbourg Verlag Munich, 1986, ISBN 3-486-22662-2, pp. 51-54. When description forms of different phases of the circuit design are compared to one another, then the circuits underlying the description forms are thereby compared.
In the framework of generating models, circuits that derive from the respective design steps are imaged onto finite automatons. A determination regarding the extent to which inputs and outputs of the automatons are to be allocated to one another follows (input/output matching). Whether identical input values also lead to identical outputs in the automatons is examined in view of this allocation. When this is not the case, a diagnosis is produced that allows the user to analyze the fault.
T. Filkorn, Symbolische Methoden für die Verifikation endlicher Zustandssysteme, Dissertation, Institut für Informatik at the Technical University, Munich, 1992, pp. 82-97. discloses a method with the object of simplifying a product machine, i.e. a combination of two automatons. The set of all status transition functions is thereby investigated and resolved into sub-sets of functions that behave identically on the set of obtainable statusses. Given automatons similar to one another, these sub-sets contain an equal number of functions from both automatons and are even often two-element, so that the allocation of the operands proceeds therefrom. One disadvantage of this method is comprised therein that differences between the two automatons do not lead to a usable result. When two status transition functions that logically belong together differ, then a correct allocation does not occur.
What is understood by status coding is a representation of a circuit in the form of an automaton, whereby this automaton comprises statusses and status transition functions.
A structural comparison of two circuits is a matter of a comparison of the combinatorial logic representing the circuit, given the assumption that the status codings of both circuits have occured in the same way.
In a sequential comparison, identical input/output behavior of two circuits is verified, whereby the respective circuits can exhibit different status.
Structurally identical automatons exhibit the same status; structurally similar automatons exhibit nearly identical status.
What is understood below by a resolution is a set that is composed of disjunctive sets. A group is an element of a resolution, whereby this element again represents a set. A sub-resolution is a sub-set of a resolution. A refinement (of a resolution) derives from the wording as a “finer” subdivision of the resolution. The relationship that has been presented is explained on the basis of a brief example:
Basic set:
{a, b, c, d, e}
Resolution:
{{a, b}, {c, d}, {e}}
Group:
{a, b] or {c, d} or {e}
Sub-resolution:
for example, {{a, b}, {e}} or
{{a,b}} or
{{c,d}, {e}}
Refinement:
{{a}, {b}, {c, d}, {e}}
SUMMARY OF THE INVENTION
An of the invention is to create a method for comparing electrical circuits, to thus not have to completely cover the design process, and, given different but structurally automatons, to assure an efficient comparison on the basis of an abstraction of status transition functions of the automatons, which describe the electrical circuits.
The circuits to be compared can proceed from different description forms for the design of an electrical circuit. It is to be assured that the electrical circuits corresponding to the different description forms are identical. Each description form represents a separate electrical circuit.
According to the method of the invention for comparison of electrical circuits, a representation of a first circuit is provided by a first automaton. A representation of a second circuit is provided by a second automaton. An allocation of input variables of the first automaton onto input variables of the second automaton and an allocation of output variables of the first automaton onto output variables of the second automaton is provided. A base set is provided with operands of the first and of the second automaton. Preceding from a predetermined resolution of the base set, implementing the following steps:
1) determining which data dependency exists between operands, input variables and output variables for each operand of the resolution, wherein
determining those operands and those input variables on which a status transition function of the operand is dependent, and
determining those operands and those output variables that are dependent on the operand for each operand;
2) combining those operands that are determined by identical data dependencies according to step 1) in a group of the resolution; and
3) implementing step 2) for all operands, so that a refinement of the resolution is determined.
Operands of the respective group are considered allocated to one another. A comparison of the two circuits underlying the automatons is implemented on the basis of the identified allocations.
A method for the comparison of electrical circuits is created wherein a first circuit is represented by a first automaton and a second circuit is represented by a second automaton. Input variables and output variables of the first automaton are imaged onto corresponding input variables and output variables of the second automaton. A basic set comprises operands of the first and of the second automaton. Proceeding from a resolution of the basic set, the following steps are implemented:
(1) For each operand of the resolution, a determination is made as to which dependencies exist between operands, input variables and output variables, whereby operands from a group can be distinguished from one another;
(2) those operands that are defined by identical data dependencies according to step (1) are combined in a group of the resolution and;
(3) step (2) is implemented for all operands, so that a refinement of the resolution is determined.
Operands of a group of the refinement are allocated to one another and a comparison of the electrical circuits underlying the automatons is implemented on the basis of the identified allocation.
One step for the comparison of two circuits that are respectively represented by a finite automaton to one another is comprised in the paired allocation of a respective operand of both automatons to one another, as a result whereof what status transition functions are to be compared and what operands are to be identified in the comparison (structural comparison) are determined.
A sequential comparison requires a predetermined variable ordering, i.e. a sequence, in which operands are noted and proc
Bormann Jörg
Warkentin Peter
Liu Andrea
Siemens Aktiengesellschaft
Smith Matthew
Staas & Halsey , LLP
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