Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-02-20
2007-02-20
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S030000, C714S733000, C365S201000
Reexamination Certificate
active
10723278
ABSTRACT:
In synchronization with a PLL clock PCK having a frequency four times that of an external clock ECK, n number of internal addresses IAD including an external address EAD are generated and, in synchronization with the PLL clock PCK, n bits of internal write data ITD are generated to be written into a RAM macro12. Thereafter, the external address EAD is latched, n number of the internal addresses IAD including the external address EAD are generated in synchronization with the PLL clock PCK, n bits of internal read data ITQ corresponding to n number of the internal addresses IAD are read from the RAM macro12in synchronization with the PLL clock PCK and the internal read data ITQ corresponding to the internal address IAD which coincides with a latch address LAD among n number of the internal addresses IAD is outputted.
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De'cady Albert
NEC Electronics Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Trimmings John P.
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