Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-04-13
2000-05-16
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714726, 714736, 714815, G01R 3128, G06F 1100
Patent
active
060651458
ABSTRACT:
The present invention provides a method for generating a path delay fault test for sequential logic circuits along a desired signal path implementing a two rated speed clocking scheme. Although initialization is accomplished at a reduced clock speed, two functional clock cycles are required to fully activate the desired signal transition along the selected signal path lying between designated source and destination flip-flops. Importantly, prior to the second functional clock cycle that activates the signal transition, a first functional clock cycle attempted at the rated clock speed is used to initialize at least the source flip-flop. In so doing, the automatic test equipment (ATE) that applies the test vectors is allowed to ramp-up to the rated clock speed prior to having to critically apply at the rated speed the required test vectors so as to launch the desired signal transition.
REFERENCES:
patent: 5365528 (1994-11-01), Agrawal et al.
patent: 5761215 (1998-06-01), McCarthy et al.
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5910958 (1999-06-01), Jay et al.
Lucent Technologies - Inc.
Moise Emmanuel L.
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