Method for testing non-deterministic device data

Details Method for testing non-deterministic device data Method for testing non-deterministic device data

2007-05-08

2007-05-08

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S715000

Reexamination Certificate

active

10606848

ABSTRACT:
A method for testing semiconductor devices that output non-deterministic entity information such as packet and control signals is disclosed. The method includes the steps generating test signals with a semiconductor tester and applying the generated test signals to the device-under-test. Actual output entities from the DUT in response to the applied generated test signals are captured by the tester and compared to expected output entities. If a failure is identified in the comparing step, the method defines a window of valid expected entities and compares the failed actual output entity to the window of valid expected entities. If a match occurs between the failed actual output entity and any of the expected entities in the window, the actual entity is deemed valid.

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“TRIM: Testability Range by Ignoring the Memory” by Carter et al. in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Publication Date: Jan. 1988 vol. 7, Issue: 1 On pp: 38-49 INSPEC Accession No. 3130635.

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