Method for testing integrated circuits with memory element...

Details Method for testing integrated circuits with memory element... Method for testing integrated circuits with memory element...

2005-04-26

2005-04-26

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S724000, C714S718000, C714S733000, C716S030000

Reexamination Certificate

active

06886122

ABSTRACT:
A method for testing an integrated circuit having memory elements which are written and/or read via an access path to the memory elements from a terminal external to the circuit. A boundary scan chain is activated to impose and/or observe logic levels on the integrated circuit inputs/outputs.

REFERENCES:
patent: 5509019 (1996-04-01), Yamamura
patent: 5631911 (1997-05-01), Whetsel, Jr.
patent: 5701308 (1997-12-01), Attaway et al.
patent: 5983379 (1999-11-01), Warren
patent: 6085336 (2000-07-01), Swoboda et al.

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