Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-08-15
2004-03-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06704893
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method for testing integrated circuits with an automatic test equipment.
Integrated circuits (IC) include generally a great number of electronic components, usually more than several hundred thousands. As the design and manufacture of such circuits are very complex operations, automatic tools are available for this design and manufacture. For instance, software design tools are available to establish schematic diagrams of the desired integrated circuit and simulation software (or simulator) is also used to check the operation of the circuit before its manufacture.
After manufacture, automatic test equipments (ATE) are available for testing the operation and the possible defects of the integrated circuit. The test consists in the application of test signals to input pins and in the measurement of the corresponding signals obtained at the output pins in order to check whether they have or not the expected values. More precisely, at a given time, a set of signals.(or values) is applied to the input pins and, after certain delay, for instance 30 nanoseconds (ns), a new set of values is applied to the input pins, etc. The timings of the signals and the delays are variable according to the test to be performed.
A set of values at a given time on the inputs is designated as a vector and the succession in time of vectors is called a test pattern.
The test patterns are established during the design of the circuit with the help of the simulator or automatic test pattern generators.
The timings of one signal, to be applied to one input, or to be detected at one output, is called here a “time-plate”. In other words, a time-plate is a succession of times at which signal changes occur. For instance, a time-plate is 0 ns, 10 ns, 50 ns for a period of 100 ns.
Generally, a test pattern comprises a great number of time-plates, typically from 40 to 100. Each time-plate is controlled by a timing generator (sometimes called a time-set) which is a physical device inside the automatic test equipment. Each timing generator must also control the signal values.
But this automatic test equipment has a limited number of timing generators. Usually, the number of time-plates used by a test program or pattern exceeds the number of timing generators available in the automatic test equipment. In order to cope with this discrepancy, the ATE is programmed in order to work in several steps. During a first step, the ATE uses all the available timing generators and during a further step, or several further steps, the timing generators are reused in order to implement all the time-plates which are necessitated by the test program of the integrated circuit under test.
To reuse a timing generator means to reprogram it in order that it corresponds to the timings of the time-plate and to the new signal values.
For instance if the ATE has 16 timing generators and the test program involves 40 different time-plates, during a first step, 16 time-plates are implemented on the 16 available timing generators; during an intermediate step, the 16 timing generators are reprogrammed in order to implement 16 other time-plates which are used during a second step of the test program; afterwards, during a further intermediate step, 8 timing generators are reprogrammed to implement the remaining 8 time-plates which will run during the last step of the test program or pattern.
SUMMARY OF THE INVENTION
The invention starts from the recognition that the testing time depends on the way the timing generators are reprogrammed in the ATE. In the example above where an ATE has 16 available timing generators and the number of time-plates of the test program is 40, the number of possible mappings between timing generators and time-plates is the number of possible combinations of m=16 timing generators among n=40 time-plates, i.e. C
n
m
. This number C
40
16
is greater than 60 billions. Each of the possible combinations requires different testing times. The actual number of possibilities is usually less than C
n
m
because there are some restrictions in the choice of the combinations. For instance, some tests must be performed before others. However, in spite of these restrictions, the number of possible combinations is very big.
According to known technologies, the choice of the combinations is realized “manually”, i.e. left to the appreciation of a programmer. It has been observed by the inventors that the testing time may vary in significant proportions in function of the selected combinations.
Therefore, the invention provides a method for reusing the timing generators which minimizes the testing time. It is to be noted that the prior art does not address this problem and, for this reason, does not provide any method for minimizing the testing time in case the number of timing generators is inferior to the number of time-plates.
The invention concerns a method for testing integrated circuits by the use of an automatic test equipment, the testing consisting in applying to each input pin signals at determined timings and in detecting the output signals at the output pins at predetermined timings, wherein each succession of timings, or time-plates, for an input pin and the corresponding output pin is controlled by a timing generator in the automatic test equipment and wherein, when the number n of time-plates is superior to the number m of timing generators, the test is realized in several steps, timing generators being reused for implementing other time-plates during a second or further step. It is characterized in that, in order to minimize the testing time, the timing generators which are reused during the second step are timing generators which impose a minimum number of programming changes from the time-plate implemented during the first step to the time-plate implemented for the second step.
A reprogramming change is a change of timing and/or a change of format. For instance, if one timing generator is programmed for a time-plate for which the timings are 0, 20, 50 ns for instance and if there is another time-plate with the same timings which has not been implemented during the first step of test, then, this timing generator will be reused with the same time-plates and there will be no time required for the reprogramming. If there is no further time-plate with the same timings but, instead, for instance, a time-plate with 0, 20, 70 ns and another time-plate with 0, 30, 70 ns, then the first one will be selected because it necessitates only one change (from 50 to 70 ns) of time parameter instead of two changes of time parameters (from 20 to 30, and from 50 to 70), in the second case.
In fact, it has been observed that the smaller the number of time and signal parameters to be changed, the smaller is the time for the change and, therefore, the testing time is the smaller.
With this method, the testing time may be reduced about 20% with respect to the testing time obtained with the mapping of time-plates to timing generators realized “manually”, i.e. left to the appreciation of the programmer.
Preferably, the number of changes to be counted for the selection of the timing generators to be reprogrammed is the addition of timing changes and of format changes.
The testing method according to the invention is preferably realized in the form of a computer program controlling the automatic test equipment. This computer program may be produced automatically by the following method:
For every possible couple of time-plates, the number of changes to be implemented in order to convert one time-plate to the other is determined, and the timing generators which will be reused from one step to the next step and the time-plates which will be implemented in these timing generators are those for which the number of changes is minimum in order to convert the time-plate used during the said one step to the time-plate used during the next step.
Preferably, the said number for all couples are kept in a memory in order to be used sequentially.
The couples of time-plates may have the form of a
Bauwens Peter
Chichkov Anton
Alcatel
Britt Cynthia
De'cady Albert
Sughrue & Mion, PLLC
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