Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-02-13
2007-02-13
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10307401
ABSTRACT:
A method for testing a plurality of functional circuit blocks of a system LSI, including dividing the plurality of functional circuit blocks into at least a first test group and a second test group, wherein the first test group is tested before the second test group and wherein testing of a functional circuit block in the second test group is started immediately after testing of a functional circuit block in the first test group is finished.
REFERENCES:
patent: 5161160 (1992-11-01), Yaguchi et al.
patent: 5673274 (1997-09-01), Yoshida
patent: 6625784 (2003-09-01), Ohta et al.
patent: 6763485 (2004-07-01), Whetsel
Chase Shelly
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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