Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-18
2005-01-18
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000
Reexamination Certificate
active
06845479
ABSTRACT:
A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FNand then forming a vector set TN−1and then simulating the vector set TN−1against the fault list FN. Any vector from the set TN−1which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set TF.
REFERENCES:
patent: 5983381 (1999-11-01), Chakradhar et al.
patent: 6052809 (2000-04-01), Bowden
patent: 6067651 (2000-05-01), Rohrbaugh et al.
patent: 20020059546 (2002-05-01), Yonetoku
NN73033038: (Random DC Functional Test Pattern Discriminator; IBM Technical Disclosure Bulletin, Mar. 1973).*
Smith et al., “System Dependability Evaluation via a Fault list generation algorithm,” Aug. 1996, IEEE Transactions on Computers vol. 45 No. 8, pp 974-979.*
Pomeranz et al., “On static compaction of test sequences for synchronous sequential circuits,” Jun. 1996, 33rd Design Automation Conference Proceedings 1996., pp 215-220.*
Arlat et al., “Fault injection for dependability validation of fault-tolerant computer systems,” Jun. 1989, Nineteenth International Symposium on Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., pp 348-355.*
Chang et al., “Test set compaction for combinational circuits,” Nov. 1992, First Asian Test Symposium, 1992. (ATS '92), Proceedings., pp 20-25.*
Kajihara et al. “On compacting test sets by addition and removal of test vectors,” Jun. 1994, 12th IEEE VLSI Test Symposium, 1994. Proceedings., pp 202-207.*
Pomeranz et al. “Static Compaction for two-pattern test sets” Nov. 1995, Proceedings of the Fourth Asian Test Symposium 1995., pp 222-228.*
Pomeranz et al. “Dynamic Test Compaction for synchronous sequential circuits using static compaction techniques,” Jun. 1996, Proceedings of Annual Symposium on Fault Tolerant Computing, 1996., pp 53-61.*
Pomeranz et al. “An Approach for improving the levels of compaction achieved by vector omission,” Nov. 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design 1999. Digest of Technical Papers., pp 463-466.*
Hsiao et al. “Fast static comapction algorithms for sequential circuit test vectors” Mar. 1999, IEEE Transactions on Computers, vol. 48 No. 3, pp 311-322.*
Hsiao, M.S.; Rudnick, E.M.; Patel, J.H., Fast static compaction algorithms for sequential circuit test vectors, Mar. 1999, IEEE Transactions on Computers, vol.:48 Issue: 3, pp. 311-322.
Gifford, Krass, Groh Sprinkle, Anderson & Citkowski, P.C.
Lamarre Guy J.
Tality UK Limited
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