Method for testing field programmable gate arrays

Details Method for testing field programmable gate arrays Method for testing field programmable gate arrays

1996-10-11

1999-11-23

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550017, G06F 1100

Patent

active

059919078

ABSTRACT:
A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. Specifically, the FPGA under test may be configured to act as an iterative logic array wherein a first group of programmable logic blocks are configured as test pattern generators, output response analyzers and helper cells, and a second group of programmable logic blocks are configured as blocks under test. The blocks under test are then repeatedly reconfigured in order to completely test each block under test in all possible modes of operation. The first and second groups of programmable logic blocks are then repeatedly rearranged so that all the programmable logic blocks are established as blocks under test at least once. Following the rearrangement, the repeated reconfiguration of the blocks under test is performed once again.

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