Method for testing field programmable gate arrays

Details Method for testing field programmable gate arrays Method for testing field programmable gate arrays

1997-11-20

1999-12-14

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550017, G06F 1100

Patent

active

060031506

ABSTRACT:
A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. This is followed by the steps of initiating the built-in self-test, generating test patterns with the programmable logic blocks and analyzing a resulting response to produce a pass/fail indication with the programmable logic blocks. More specifically, the configuring step includes establishing a first group of programmable logic blocks as test pattern generators and output response analyzers and a second group of programmable logic blocks as blocks under test. The blocks under test are then repeatedly recongifured in order to completely test each block under test in all possible modes of operation. The programming of the first and second groups of programmable logic blocks is then reversed and the testing of each new block under test is then completed.

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