Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-05-24
2005-05-24
Chung, Phung My (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S734000
Reexamination Certificate
active
06898747
ABSTRACT:
The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals (106a-106n) are input from a test device (105) into the circuit unit (100) to be tested via a connecting unit (104), the circuit unit (100) to be tested is tested by means of the test input signals (106a-106n) in order to obtain corresponding test output signals (107a-107n) which indicate an operability of the circuit unit (100) to be tested, a gate unit (101) is connected to the connecting unit (104) by means of a first test mode switching unit (102) and of a second test mode switching unit (103), in such a manner that the test output signals (107a-107n), after being logically combined in the gate unit (101), are provided as a combined test output signal (109) via a single output line (110), and the combined test output signal (109) is output to the test device (105).
REFERENCES:
patent: 4625310 (1986-11-01), Mercer
patent: 5594694 (1997-01-01), Roohparvar et al.
Chung Phung My
Infineon - Technologies AG
Jenkins & Wilson & Taylor, P.A.
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