Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-11-28
2006-11-28
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S734000
Reexamination Certificate
active
07143325
ABSTRACT:
The invention provides a test device for testing circuit units (101a–101n) to be tested, having connecting units (106a–106n) for connecting the circuit units (101a–101n) to be tested to the test device, a test system (100) and an output unit (108) for outputting test result data, the test device having a determining unit (103) for determining those of the measurement data (110a–101n) which correspond for a predeterminable number of circuit units (101a–101n) to be tested, and for defining the corresponding measurement data (110a–110n) as the expected data (111); and comparison units (104a–104n) for comparing the measurement data (110a–110n) generated by the circuit units (101a–101n) to be tested in a manner dependent on the test data (112) written in with the expected data (111) in order to obtain comparison data (115a–115n).
REFERENCES:
patent: 6480978 (2002-11-01), Roy et al.
patent: 6559671 (2003-05-01), Miller et al.
patent: 2001/0025227 (2001-09-01), Ajiro
patent: 2002/0133774 (2002-09-01), Inoue
patent: 2003/0071649 (2003-04-01), Dankowski et al.
patent: 101 50 441 (2003-04-01), None
Chung Phung My
Infineon - Technologies AG
Maginot Moore & Beck
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