Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-24
2007-04-24
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C716S030000
Reexamination Certificate
active
10609387
ABSTRACT:
The present invention relates to a method for testing a chip, particularly to a method for testing chip configuration settings, essentially installing the chip on a main board after the chip fabrication is finished. The test comprises starting power first of all, a power on self test being performed by the system; loading a BIOS program, wherein the BIOS program includes a configuration test process; testing the configuration settings of the chip by the configuration test process; inputting test data in turn; then enabling registers corresponding to the chip configuration space depending on the test data, for starting the chip operation; obtaining the data, produced by the chip operation, to be compared with an expected result, in order for performing the verification of chip configuration settings at the final stage before the actual chip operation is started, so as to speed the development and modification for the chip.
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“Configuration Self-Test in FPGA-based Reconfigurable Systems” by Quddus et al. IEEE International Symposium on Circuits and Systems, 1999. Publication Date: Jul. 1999 vol. 1, pp. 97-100 ISBN: 0-7803-5471-0 INSPEC Accession No. 6382155.
Britt Cynthia
Rosenberg , Klein & Lee
Via Technologies Inc.
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