Method for testing at least one arithmetic unit installed in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S025000, C714S030000, C714S031000, C714S715000, C714S724000, C714S726000, C714S727000, C714S729000, C714S733000, C714S736000, C714S742000

Reexamination Certificate

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07913142

ABSTRACT:
A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

REFERENCES:
patent: 6243665 (2001-06-01), Nagoya et al.
patent: 6760874 (2004-07-01), Cote et al.
patent: 6983398 (2006-01-01), Prabhu
patent: 2007/0043488 (2007-02-01), Avery et al.
patent: 0 548 585 (1993-06-01), None
Messmer, H.P.: “The Indispensable PC Hardware Book, Second Edition” 1995, Addison-Wesley Publishing Comp., Wokingham, UK, pp. 211, 220, 259-266, 347; and 534-535.

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