Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1995-12-27
1999-09-28
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
39550005, G06F 1100
Patent
active
059580771
ABSTRACT:
A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit. The STM offers numerous advantages over prior art methods namely, (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the asynchronous circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM enforces a fundamental mode of operation during test generation. Experimental results on several benchmarks show that the STM method generates high fault coverage tests with no test invalidation.
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Banerjee Savita
Chakradhar Srimat T.
Roy Rabindra K.
Beausoliel, Jr. Robert W.
Brosemer Jeffery J.
Feig Philip J.
Iqbal Nadeem
Isztwan Andrew G.
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