Method for testing an integrated semiconductor memory with a...

Details Method for testing an integrated semiconductor memory with a... Method for testing an integrated semiconductor memory with a...

2007-03-27

2007-03-27

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S742000

Reexamination Certificate

active

11095670

ABSTRACT:
An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

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HYB25D266[400/800/160]B[T/C](L) 256-Mbit, Double Rata Data SDRAM, Die Rev. B.; Data Sheet, Jan. 2003, V1.1.

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