Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-09-18
2001-10-23
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06308291
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the electronics field. More specifically, the invention relates to a method for testing an electronic circuit in which the actual state of circuit components which have previously been activated on a test basis after an initial initialization is compared with a setpoint state.
Such a method is, for example, the so-called scan method used in particular for testing integrated circuits.
Circuits that are enabled for testing in accordance with the scan method must be capable of being placed in a scan mode of operation in which selected circuit components, such as, for example, all the flip-flops of the circuit, are connected in such a way that they can be placed individually in specific initial states by means of a test device provided outside the circuit to be tested, and that their current state can, when necessary, be read out by the test device. This can be achieved when flip-flops are used as selected circuit components by virtue of the fact that the flip-flops are connected one behind the other in series in a scan mode of operation, the input terminal of a respective flip-flop being connected to the output terminal of the flip-flop located in front of it in series, and the output terminal of a respective flip-flop being connected to the input terminal of the flip-flop which comes after it in the series. Such an arrangement is also referred to as a scan chain.
Such a scan chain, to be more precise its elements formed by flip-flops in the example under consideration, can be initialized relatively easily. A signal applied to the input terminal of the first flip-flop of the scan chain, to be more precise the state of the relevant flip-flop which comes about in response thereto, is namely passed on from flip-flop to flip-flop with the clock of a clock signal applied to the flip-flops; with each clock pulse each flip-flop of the scan chain assumes the state of the flip-flop located in front of it in the scan chain.
If the x
th
flip-flop of the scan chain is placed in the state A, all that is necessary is “merely” to apply a signal to the input terminal of the first flip-flop of the scan chain. The signal places that flip-flop and the flip-flops connected downstream in the state A. Thereby, x clock pulses are applied to the scan chain (all the flip-flops of said chain).
Conversely, at the last flip-flop of the scan chain it is possible to read out the states of the individual flip-flops sequentially at a specific time.
If the scan chain contains n flip-flops, the circuit test is carried out according to the scan method as follows: firstly, the circuit is placed in the scan mode of operation, as a result of which the scan chain is formed. That scan chain is placed in a defined initial state by sequentially applying n input signals and n clock pulses. Then, the circuit is placed in a normal mode of operation; for this purpose the circuit is moved out of the scan mode of operation, the scan chain (the series connection of the flip-flops) is broken up. In the normal mode of operation, the circuit is briefly operated normally on a test basis. The time during which the circuit is operated normally is preferably defined by a number of clock cycles. This number of clock cycles is preferably very small (for example 1). In the time during which the circuit is operated normally, at least some of the states of the initially initialized flip-flops change, it being possible to determine from the way in which the circuit to be tested functions according to the regulations the (setpoint) state the flip-flops ought to be in at a respective time. After the circuit has operated normally for a predetermined number of clock cycles, it is returned to the scan mode of operation, as a result of which the flip-flops can be reconnected to form the scan chain. If the flip-flops which are connected in this way have clock signals applied to them in this state, data which represent the (actual) state of the flip-flops of the scan chain at the time when normal operation ends are pushed out sequentially at the end of the scan chain (from the output terminal of the last flip-flop of the scan chain) in time with the clock signals. If the actual state, determined as described, of the flip-flops of the scan chain is then compared with the known setpoint state of the chain, it is possible to determine whether or not the circuit to be tested is running without faults.
Tests that function in this way or similarly make it possible, in a relatively simple way, to test comprehensively even very complex circuits within a very short time. However, experience shows that under unfavorable conditions circuits which are functioning satisfactorily may be categorized as faulty. This is understandably a disadvantage which needs to be eliminated.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of testing electronic circuits, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables dependable testing which avoids incorrect fault detection, i.e. which assures that only faulty circuits are categorized as faulty.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of testing an electronic circuit, which comprises:
initializing a number of circuit components;
simultaneously activating essentially only those circuit components on a test basis of which interaction is expected in a given context; and
reading out an actual state of the circuit components to be tested, and comparing the actual state of the circuit components with a setpoint state.
Interaction, according to the design of the circuit, of cooperating circuit components, which may be, for example, the flip-flops but also other and/or more extensive components of the circuit to be tested is not to be expected, inter alia, when the clock signals with which the individual circuit components are to be clocked have an excessively large offset from one another or clock skew when operating on a test basis during the circuit test. This is as a rule particularly pronounced when the clock signals are produced by means of various clock signal generators.
These and other inadequacies in the interaction of circuit components can be avoided if circuit components which do not interact, or possibly do not interact, in accordance with the circuit design in the case of the activation of the circuit on a test basis when it is being tested are not activated simultaneously.
The circuit components which are not activated are preferably simply not supplied with clock signals.
During such partial operation of the circuit, precisely reproducible results (circuit component states) are always obtained; this reliably excludes the possibility of the states of the circuit components (the elements of a scan chain) which are of interest and on which the evaluation of the test is based being able to vary due to random factors.
The fact that specific circuit components do not interact according to the regulations during the circuit test cannot be interpreted as meaning that the circuit is faulty; it is merely the particular circumstances of the activation of the circuit on a test basis, in particular the extraordinary and only extremely brief activation which causes specific circuit components to interact in a way which is not according to the circuit layout prescriptions.
The comparison of the setpoint states of the circuit components which are activated and of the actual states of the components consequently allows the following conclusions to be drawn regarding the freedom from faults or faultiness of the circuit to be tested, with a degree of probability which borders on certainty. In particular, the possibility of circuits which are operating free of faults being categorized as faulty is essentially excluded.
In other words, of the circuit components to be tested, essentially only in each case those circuit components are operated simultaneously which, under the gi
Kock Ernst-Josef
Schneider Peter
Chase Shelly A
De'cady Albert
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft AG
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