Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-28
2002-08-13
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C438S513000, C438S528000
Reexamination Certificate
active
06432780
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device, and more particular to a method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping.
BACKGROUND OF THE INVENTION
Fabrication of metal-oxide-semiconductor (MOS) transistors is well-known for the skills in the art. The manufacturing process begins by lightly doping a single crystalline silicon substrate with n-type or p-type species. Active areas of the substrate in which the transistors and other active devices will reside are then isolated from other active areas with isolation structures. Isolation structures may comprise shallow trenches in the substrate that are filled with a dielectric. Isolation structures may alternatively comprise local oxidation of silicon (LOCOS) structures. A gate dielectric layer (i.e., silicon dioxide) is then formed upon the substrate by thermally oxidizing the silicon-based substrate. A gate conductor is formed by depositing polysilicon upon the gate dielectric, followed by patterning the polysilicon using typical masking and etching techniques. Subsequently, the polysilicon gate conductor and source/drain regions arranged within the substrate on opposite sides of the gate conductor are concurrently doped with a high dosage of n-type or p-type dopants. If the impurity dopant is p-type, then the resulting transistor is referred to as a PMOS device.
The resistivity of the polysilicon gate conductor is reduced by the introduction of impurities into the structure. Enough dopants are introduced so that the sheet resistance of the gate conductor is reduced to, in some instances, less than approximately 500 ohms/sq. In an ion implantation process, the depth at which the dopants are implanted can be controlled by adjusting the energy provided to the ions by the ion implantation equipment. However, the minimum depth of implantation is limited to between 200 .ANG. and 400 .ANG., because the energy of each ion is typically too large to permit a lesser depth of implantation.
Subsequent processing steps may require heating of the semiconductor topography. For example, a post-implant anneal is often performed to position and activate the dopants implanted into the source/drain regions and the gate conductor. Dopants with a high diffusivity typically migrate to greater depths within the polysilicon gate than dopants with a low diffusivity. For instance, boron which is commonly used to dope the polysilicon gate and the source/drain regions of a PMOS device undergoes fast diffusion. Unfortunately, boron readily migrates during heat treatment and may diffuse from the gate conductor through the gate oxide and into the channel region of the transistor. Boron penetration into the channel can lead to undesirable effects, such as an increase in electron trapping, a decrease in low-field hole mobility, degradation of the transistor drive current, and increased subthreshold current.
Hence, while critical dimension is scaling down to 0.18 &mgr;m, the thickness of the gate dielectric layer is thinner than 20 ANG., and therefore, boron penetration effect is more significant. It is important to suppressing boron penetration through the gate dielectric layer into the device channel region that causes threshold voltage change and effects device operation.
SUMMARY OF THE INVENTION
The present invention provides a method of suppressing boron penetrating a gate dielectric layer by pulsed nitrogen plasma doping, comprising the following steps. A semiconductor substrate having a channel region is provided. A pulsed nitrogen plasma doping step is then performed to dope nitrogen ions into the surface layer in the channel region. A nitrogen annealing step is optionally performed after the pulsed nitrogen plasma doping step to enhance the doping result of nitrogen ions. A thermal oxidation step is performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate.
According to the method of fabricating the gate dielectric layer of the present invention, an oxynitride containing thin film is formed over the channel region. Since the nitrogen ions doped in the surface layer in the channel region can produce a dense structure to provide a barrier to effectively suppress boron penetrating through the gate dielectric layer into the channel region, and therefore, electric property change of transistors causing from boron penetrating can be prevented.
REFERENCES:
patent: 6093661 (2000-07-01), Trivedi et al.
Chen Jack
Frazer & Murphy LLP
Goldstein Powell
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