Method for self-aligned vertical double-gate MOSFET

Details Method for self-aligned vertical double-gate MOSFET Method for self-aligned vertical double-gate MOSFET

2000-11-09

2002-04-16

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S156000, C438S162000, C438S166000

Reexamination Certificate

active

06372559

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing, and more particularly to a method for forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) wherein a silicon-on-insulator (SOI) substrate is employed in fabricating the same.
BACKGROUND OF THE INVENTION
It is well known that a dual gate or double-gate MOSFET device has several advantages over conventional single-gate MOSFET devices. Specifically, the advantages for double-gate MOSFET devices over their single-gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel double-gate MOSFET device and has shown that the double-gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET). Moreover, improved short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. Another advantage of double-gate devices over their single-gate counterparts is that improved threshold slope can be obtained.
Previous efforts of fabricating double-gate MOSFETs generally fall into one of the following three categories:
(a) Etch silicon into a pillar structure and deposit gates around it.
(b) Make a conventional single-gate MOSFET, then use either selective epitaxy or bond-and-etch-back techniques to form the second gate.
(c) Start with a thin silicon-on-insulator (SOI) film, pattern a strip and dig a tunnel across it by etching the buried oxide. Then, deposit gate electrodes in the tunnel and on top of the SOI film.
Notwithstanding which technique is employed, it is important that the gate region of the double-gate MOSFET is self-aligned. This is particularly important since failure to achieve such alignment results in excessive parasitic capacitance, and decreased drive current. Moreover, none of the prior art methods of fabricating double-gate MOSFETs decouple the gate contact implant/anneal step from the processing steps used in forming the intrinsic device; therefore, additional performance enhancement, which is typically associated with such decoupling, is not obtained from prior art methods. A further problem with conventional methods of forming double-gate MOSFET devices is that none of the conventional methods provide a satisfactory means for constructing a well-controlled vertical-asymmetrical channel-doping profile.
Examples of prior art methods of producing self-aligned double-gate MOSFETs include:
H. S. P. Wong, et al., “Self-Aligned (top and bottom) Double-Gate MOSFET with a 25 nm Thick Si Channel”, IEDM Tech Dig., p. 427 (1997)—Although the Wong, et al. disclosure provides a method of forming a self-aligned double-gate MOSFET, the device provided therein is planar. Moreover, the gate is formed from in-situ doped CVD polysilicon which makes it not fully compatible with CMOS applications. Additionally, the gate length is controlled by lithography and etching which makes it difficult to achieve small gate lengths.
J. H. Lee, et al., “Super Self-Aligned Double Gate (SSDG) MOSFETS utilizing Oxidation-Rate Difference and Selective Epitaxy”, IEDM Tech Dig., p.71 (1999)—This prior art reference provides self-aligned gate regions, but as is the case above, the gate length is controlled by lithography and a planar device is obtained.
J. M. Hergenrother, et al. “The Vertical Replacement-Gate (VRG) MOSFET: A 50 nm Vertical MOSFET with Lithography-Independent Gate Length”, IEDM Tech.
Dig., p.75 (1999)—This reference provides gates that are self-aligned and vertical. Moreover, this reference determines it gate length by film thickness rather than lithography. Despite these advantages, the Hergenrother, et al. reference uses in-situ doped polysilicon deposition which makes its compatibility with CMOS processes in question.
In view of the drawbacks mentioned hereinabove with prior art methods for fabricating double-gate MOSFET devices, it would be beneficial if a new method was developed that is relatively simple, yet effective in fabricating double-gate devices which is capable of forming self-aligned gates and a well-controlled vertical asymmetrical channel-doping profile, while decoupling the gate contact implant/anneal from the processing steps used in forming the intrinsic device.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of forming a self-aligned vertical double-gate MOSFET device.
A further object of the present invention is to provide a method of forming a double-gate MOSFET device wherein the gate contact implant/anneal is decoupled from the processes used for forming the intrinsic device.
A yet further object of the present invention is to provide a method of forming a double-gate MOSFET device in which a well-controlled vertical-asymmetrical channel-doping profile is obtained.
An even further object of the present invention is to provide a method of forming a double-gate MOSFET device in which a SOI substrate is employed instead of a conventional bulk Si-containing substrate.
These and other objects and advantages are achieved by employing the inventive method which includes the steps of:
(a) growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type;
(b) patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate;
(c) forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon;
(d) removing oxide on horizontal surfaces which interface with said Si-containing bottom layer;
(e) recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon;
(f) forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed;
(g) selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm
−2
or greater;
(h) selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer;
(i) removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening;
(j) etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and
(k) saliciding any exposed silicon surfaces.
The inventive method described above provides the following advantages:
(1) All gate and drain anneals may be optimized for highest possible activation. The gate and drain anneals are done prior to intrinsic implants.
(2) Since the device is vertical, the source/drain implants do not rely on lateral diffusion in order to achieve overlap with the gate. Therefore, the source and drain will have lower resistance for a given junction depth as compared to standard laterally diffused source/drain extensions.
(3) Moreover, the vertical design allows for optimized channel implants that is vertically graded with larger concentrations present near the source. This lateral-channel asymmetry is known to provide a performance enhancement relative to conventional symmetrical profiles. In standard planar CMOS processes, achieving lateral asymmetry is very difficult since multiple spatial orientations of device are present in any chip design. Furthermore, since planar devices rely on lateral diffusion of dopants to form profiles located specifically near the source and drain regions such lateral asymmetry is inherently harder to control. This feature is additive to other details discussed herein.
(4) All proce

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