Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-06
2001-11-27
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S630000, C438S649000, C438S655000
Reexamination Certificate
active
06323130
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to complementary metal oxide semiconductor (CMOS) manufacturing, and more particular to a method for limiting silicon consumption and reducing bridging during silicide contact formation by using a metal silicon alloy as the starting material for the silicide contact.
BACKGROUND OF THE INVENTION
One type of material commonly employed in fabricating ohmic contacts is metal silicides such as cobalt silicide. Cobalt silicide and other metal silicides are typically fabricated using a conventional self-aligned silicide (salicide) process, wherein a blanket TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over the exposed silicon regions (source, drain and gate) of transistors in USLI integration. A selective wet etch is employed to remove the TiN cap and the non-reacted cobalt left over the oxide or nitride regions. The cobalt monosilicide is then subjected to a second anneal which converts the monosilicide into a cobalt disilicide layer. The cobalt disilicide phase has a lower resistance than the cobalt monosilicide phase.
The above self-aligned silicide process cannot be performed using a single anneal because of the diffusion of silicon (Si) atoms in the cobalt (Co) film along the sidewalls of the transistor. If the first anneal is at too high a temperature, Si can diffuse in the cobalt over the oxide
itride regions of the device and will not be removed by the etch so that the source and drain areas become shorted to the gate. This phenomenon is known in the art as bridging. The self-aligned silicide process relies on the selective wet etch for removing any left over metal alloy or metal from the exposed nitride/silicon regions. As the device dimensions are further reduced, the constraints on the Si diffusion will become more stringent.
Moreover, and as one skilled in the art is aware, the silicide formation consumes a considerable amount of silicon. The thickness of Si consumption for a Co disilicide film is 3.6 times that of the initial cobalt film. As the junction depth of active regions becomes shallower, this large Si consumption becomes a problem.
In view of the above drawbacks with prior art salicide processes, there is a continued need for developing a new and improved method that is capable of limiting silicon consumption and reducing bridging during metal silicide formation.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of substantially limiting Si consumption during the formation of low resistivity metal silicide contacts.
Another object of the present invention is provide a method of substantially reducing Si diffusion that may cause bridging during the formation of low resistivity metal silicide contacts.
A further object of the present invention is to provide a method wherein the anneal temperature used in forming a substantially non-etchable metal silicide layer is considerably lower compared to conventional salicide processes. The term “substantially non-etchable” denotes a material that is more difficult to etch than the starting metal silicon alloy or the pure metal in the etchant solutions mentioned hereinbelow.
A still further object of the present invention is to provide a method wherein the annealing step prior to the selective etching is capable of forming a metal rich silicide layer that is substantially non-etchable.
These and other objects and advantages are achieved in the present invention by utilizing a metal silicon alloy as the starting material in fabricating metal silicide contacts. The use of a metal silicon alloy as the silicide starting material significantly limits the Si consumption and reduces bridging during metal silicide contact formation. Bridging is limited since the metal silicon alloy enhances the formation of a metal rich silicide phase in such a way that the temperature of the first anneal (i.e., the anneal prior to etching) can be significantly reduced.
Applicants have unexpectedly determined in this regard that the use of a metal silicon alloy reduces the temperature for the formation of the metal rich silicide phase by more than 150° C. Additionally, applicants have unexpectedly determined that the use of a metal silicon alloy provides a much wider anneal temperature range for the formation of the metal rich silicide phase as compared to prior art salicide processes. Moreover, applicants have determined that the use of a metal silicon alloy provides a substantially non-etchable film at lower temperatures than heretofore possible utilizing prior art salicide processes.
The method of the present invention which provides these unexpected findings comprises the steps of:
(a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof;
(b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy layer or pure metal;
(c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and
(d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase.
An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).
When Ni is employed as the metal, a Ni rich silicide phase is formed after annealing step (b). Annealing step (d) converts the Ni rich silicide phase into Ni monosilicide which represents the lowest resistance silicide phase of Ni. On the other hand, when Co is employed, annealing step (b) converts the Co—Si alloy layer into a Co rich silicide layer and annealing step (d) converts the metal rich silicide phase into a Co disilicide phase which represents the lowest resistance silicide phase of Co.
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C. Cabral, et al., “In-Situ X-Ray Diffractin and Resistivity Analysis of CoSi2 Phase Formation With and Without a Ti Interlayer at Rapid Thermal Annealing Rates,” Mat. Res. Soc. Symp. Proc., vol. 375, pp. 253-258 (1995).
Brodsky Stephen Bruce
Cabral, Jr. Cyril
Carruthers Roy Arthur
Harper James McKell Edwin
Lavoie Christian
Bowers Charles
Brewster William M.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Trepp Robert M.
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