Method for selectively forming strain in a transistor by a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S229000, C438S230000, C438S486000, C257SE21632, C257SE21634, C257SE21640

Reexamination Certificate

active

07906385

ABSTRACT:
A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.

REFERENCES:
patent: 7052946 (2006-05-01), Chen et al.
patent: 2004/0092063 (2004-05-01), Okumura et al.
patent: 2006/0099765 (2006-05-01), Yang
patent: 2008/0026572 (2008-01-01), Wirbeleit et al.
patent: 2008/0153221 (2008-06-01), Sridhar et al.
patent: 2009/0294866 (2009-12-01), Eller et al.
patent: 102006035646 (2008-03-01), None
patent: 102007057687 (2009-06-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 007 003.3 dated Aug. 20, 2009.
Wiatr et al., “Review on Process-Induced Strain Techniques for Advanced Logic Technologies,” Advanced Thermal Processing of Semiconductors 2007, RTP 2007, 15thInternational Conference, pp. 19-29, Oct. 2007.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 007 003.3 dated Oct. 27, 2008.

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