Method for selective growth of Cu3Ge or Cu5Si for...

Details Method for selective growth of Cu3Ge or Cu5Si for... Method for selective growth of Cu3Ge or Cu5Si for...

2000-03-13

2001-01-30

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S622000, C257S752000, C257S751000

Reexamination Certificate

active

06181013

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to copper electrical conductors formed on a conductive substrate and more particularly to passivation of an exposed surface of such a copper conductor.
2. Description of Related Art
Copper conductors formed as a Damascene structures on the top level of a semiconductor device are directly exposed to air. The formation of an oxide of copper (CuO) on the surfaces of such copper conductors makes it difficult to perform measurements during the Wafer-Accept-and-Test (WAT) process.
U.S. Pat. No. 5,420,069 of Joshi et al. for “Method of Making Corrosion Resistant, Low Resistivity Copper for Interconnect Metal Lines” shows a Cu
x
Ge
y
corrosion resistant layer over a copper (Cu) line. It describes a “corrosion resistant thin film interconnect material, comprising a bilayer formed of a copper (Cu) film over which a layer of Cu
3
Ge or copper germanium (Ge) alloy has been deposited.” In
FIG. 3B
, Joshi et al. “. . . shows Cu—Ge passivation layer 180 on all exposed surfaces of copper.” This provides “excellent passivation properties”. The preferred process described is “selective deposition of germanium over copper surfaces . . . exposing the original Cu layer (or surface) at a low pressure (0.5 Torr to 1 Torr) to a source of germanium, e.g. GeH
4
gas, in a chemical vapor deposition (CVD) reactor at temperatures ranging from about 200°-450° C. to convert the outer surface of the Cu lines to Cu(x)Ge(y) or Cu
3
Ge . . . Any Ge containing gas source, e.g. GeH
4
, GeH
6
and the like can be used . . . It is noted that by increasing the partial pressure of GeH
4
more than 0.1 Torr, the Cu(x)Ge(y) alloy can be changed to Cu
3
Ge or additional Ge can be formed.” Copper “rich phases and . . . specifically Cu
3
Ge may also be produced by plating (electrolytic and electroless), sintered powder and sputtered bilayers which are subsequently reacted.
U.S. Pat. No. 4,086,176 of Ericson et al. for “Solutions for Chemically Polishing Surfaces of Copper and Its Alloys” describes an improvement over use of a sulfuric
itric acid/chlorohydric aqueous solution as an acid bath in a high concentration as a “bright dip.” and other baths which were unsatisfactory. Ericson et al. show a solution for chemically polishing copper and copper alloys with mono- and di-substituted alkali metal salts of oxalic acid with a pH value from 3-5 combined with hydrogen peroxide accompanied by a stabilizer comprising a aliphatic fatty amine and benzotriazole and a brightener consisting of sodium lignin sulphonate.
U.S. Pat. No. 5,731,245 of Joshi et al. for “High Aspect Ratio Low Resistivity Lines/Vias with Tungsten Alloy Hard Cap” shows a CuGe CMP hard cap for a copper (Cu) plug. Joshi discusses copper/germanium barrier layers.
S. Hyme et al. “Passivation of copper by silicide formation in dilute silane”, Journal of Applied Physics, Vol. 71 pages 4623-4625, (May 1, 1992) discusses use of copper for an interconnection material for integrated circuit devices and reports that copper silicide forms upon exposure of sputtered copper films to two percent silane in nitrogen gas at various temperatures as low as 300° C. It is stated that gamma phase Cu
5
Si form first followed by formation of eta phase Cu
3
Si. Metal suicides decompose when exposed to oxidizing ambients at high temperatures leading to formation of an oxide on the surface which inhibits further decomposition and oxidation, so for copper silicides a SiO
2
layer is formed which would retard the oxidation of the underlying silicide and copper at temperatures below 450° C. for use of copper as an interconnection material. The silicide layer reportedly provides protection of the underlying copper from oxidation thereof at temperatures up to 550° C. in air. At page 4625, it is stated that “the gamma phase silicide would be expected to passivate copper interconnection lines from oxygen containing ambients, such as during SiO
2
glass insulator deposition.”
U.S. Pat. No. 5,288,456 of Aboelfotoh et al. for “Compound with Room Temperature Electrical Resistivity Comparable to that of Elemental Copper” shows a process for producing copper germanide Cu
3
Ge compound on the surface of a silicon substrate which had been treated by evacuation to a pressure of 1×10
−7
Torr for a period of time following which Ge, Ga and copper were deposited sequentially in an evacuated chamber at room temperature to avoid contact with air or oxygen. A thin film of 700 Å of germanium (Ge) was deposited on a <100> surface of the silicon substrate. Then 5-10 atomic percent of gallium (Ga) was deposited on the Ge film followed by deposition of copper (Cu) to a thickness of about 1300 Å. Then the result of the process to this point is annealed at a temperature of about 400° C. in situ for 30 minutes in vacuum. The result is a thin layer of the Ge
3
Cu compound with a thickness of about 2000 Å thickness on the surface which has 1-2% of Ga incorporated therein.
U.S. Pat. No. 5,612,254 of Mu et al. for “Methods of Forming Interconnect on a Semiconductor Substrate” describes formation of interconnect channels in a silicon dioxide layer and the forming a titanium nitride barrier followed by filling the channel with a copper conductor followed by planarizing the copper and titanium nitride barrier layer to the level of a silicon dioxide layer in which the interconnects are formed. Then the copper surface in the interconnects is covered with a silicon oxynitride passivation layer.
U.S. Pat. No. 5,744,376 of Chan et al. for “Method of Manufacturing Copper Interconnect with Top Barrier Layer” describes damascene process steps for forming copper interconnections with a lower barrier layer composed of titanium nitride, tungsten nitride, titanium tungstide or tantalum nitride and an upper barrier layer of aluminum oxide, tanatalum oxide, or silicon nitride. It is stated at Col. 2, lines 7-11 of Chan et al. that “The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.”
See patents on metal conductor wires as follows:
U.S. Pat. No. 5,818,110 of Cronin for Integrated Circuit Chip Wiring Structure with Crossover Capability and Method of Manufacturing the Same”,
U.S. Pat. No. 5,824,599 of Schacham-Diamand et al. for “Protected Encapsulation of Catalytic Layer for Electroless Copper Interconnect,
U.S. Pat. No. 5,889,328, of Joshi et al. for “Refractory Metal Capped Low Resistivity Metal Conductor Lines and Vias”, and
U.S. Pat. No. 5,891,513 of Dubin et al for “Electroless Cu Deposition on Barrier Layer by Cu Contact Displacement for ULSI Applications”.
SUMMARY OF THE INVENTION
For a copper (Cu)-damascene process, we find that a copper (Cu)-CMP planarization process is necessary and that it can require processing in an acid environment including hydrogen peroxide (H
2
O
2
) plus a slurry of a polishing agent.
An object of this invention is to provide Cu conductors which are so manufactured as to avoid Cu corrosion.
Form a copper conductor in a thin film electronic device over a conductive substrate with an ancillary surface in which a dielectric layer is formed on the ancillary surface of the conductive substrate with the dielectric layer having a top surface. Pattern the dielectric layer to etch a trench through the top surface down to the substrate. Expose a portion of the ancillary surface of the conductive substrate and form exposed sidewalls of the dielectric layer. Form a barrier layer over the ancillary surface of the conductive substrate and the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. The barrier layer forms a narrower hole in the trench. Form a copper conductor having a surface, with the copper conductor being over the barrier layer with the copper conductor overfilling the narrow hole. Remove material from the

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