Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-14
2004-06-01
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C714S724000, C714S732000
Reexamination Certificate
active
06745370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to yield improvement in integrated circuits and in particular, yield improvement in integrated circuit memory. More particularly, the present invention relates to improvements in the use of redundancy in memory arrays.
2. The Prior Art
The electrical test yield of an integrated circuit memory can be dramatically improved by the use of redundant rows and/or columns of cells that can be used in a memory in the place of a row or a column containing failing bits for the case in which the electrical test yield is limited by localized manufacturing defects. The use of redundancy in memories is well known and has been employed for many years.
As is well known, not all faults (i.e. alterations in circuit behavior) are repairable. Specifically, faults resulting from device parametric changes that affect large areas or faults that affect the chip globally such as shorts between traces that connect to power supplies with differing potential are not repairable.
A critical issue is the amount of redundancy to be incorporated in the design. It is desirable to have enough redundancy to repair most of the repairable faults. However, as more redundancy is incorporated, the area of each integrated circuit grows so that the number of dice that will fit onto a wafer decreases. Thus, beyond some level of redundancy, the number of gross dice on a wafer decrease faster than the number of dice repaired by the additional redundancy increase so that the net number of good dice after redundancy repair decreases. The goal is to choose the amount of redundancy to maximize the number of usable dice produced per wafer.
There are many repair schemes possible to employ the redundancy that is built into a part, especially if both row and column redundancy are available. For example, first all of the row redundancy could be used; then, if there are still unrepaired faults, the column redundancy would be used until either all faults were repaired or all of the redundancy was used up. Alternatively, the redundant row and columns would be employed in an alternate fashion, first a redundant row and then a redundant column, until either all faults are repaired or all available redundant cells are used. Some procedures, or algorithms, are more efficient than others, on the average, in the use of the redundant resources so that with a given level of resources, a higher fraction of the dice on a wafer are repaired.
SUMMARY OF THE INVENTION
The focus of the present invention is predicting the level of redundancy that will yield the highest number of usable (i.e. good plus repairable) dice per wafer prior to completion of the memory design so that the optimum redundancy can be designed into the product.
This invention begins by analyzing the chip layout layer by layer to identifying the regions in which a defect can cause a fault, i.e. an alteration of the circuit topology, and the relative likelihood that each fault will occur for a defect of a given size. (Each layer may be thought of as a conducting layer that may be incorrectly linked to another conductor to form a bridge fault or incorrectly broken to form a break fault.)
Once the faults are identified, the electrical output responses to a set of input stimuli are found. The responses to each fault is called a signature. In general, several faults may have the same signature. Examples of signatures are a failing row, a failing column, a single bit failure, etc.
The faults for each defect size on each layer are weighted by the relative probabilities of the defect sizes. It is commonly found that the probability of the defect sizes is proportional to &lgr;
−3
where &lgr; is the diameter of the defect, but other weightings can be used if it is found that they better describe the distribution for a given technology. The weighted fault distributions are summed over defect sizes and process layers to arrive at a single distribution of signatures representing the probabilities of the signatures occurring taking into account defects of all sizes occurring on all process layers. This distribution is stored for use in later calculations.
Of course, more than one signature can occur on a single die. This requires that the signature distribution be used to calculate the probability of various combinations of signatures. For each combination of signatures, the redundancy algorithm is applied to find the number of redundant elements required to repair that combination. Since the probability of each combination is known, the fraction of the defect combinations that can be repaired for each level of redundancy is determined, which determines the fraction of the available dice that are usable for each level of redundancy.
Separately, the area penalty to the die for various levels of redundancy can be estimated. Typically, there is a fixed area cost for the implementation of any redundancy plus a term that increase with the level of redundancy. The fixed term arises from the overhead of the circuitry required to implement redundancy. The variable area comes from the extra rows and/or columns inserted to provide the redundant memory cells and the growth in the size of the redundancy circuitry as more redundancy is included. Once the area penalty for redundancy is estimated, the total number of dice on each wafer can be calculated as a function of the level of redundancy.
Combining the number of available dice per wafer with the fraction of available dice that are usable provides a prediction of the number of usable dice per wafer. The level of redundancy is chosen to maximize this number.
An additional benefit can be gained from the procedure outlined in this invention is that with a small variation, the redundancy repair algorithm can also be optimized. For redundancy levels at or slightly below the level determined to be optimum, the number of usable dice per wafer can be determined with the available redundancy applied with the different redundancy algorithms to select the algorithm that maximizes the number of usable dice.
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D.Y. Lepejian et al., An Automated Failure Analysis Methodology for Repeated Structures, 12thIEEE VLSI Test Symposium, pp. 319-324, Apr. 1994.*
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J. Segal et al., “A Framework for Extracting Defect Density Information for Yield Modeling from In-line Defect Inspection for Real-time Prediction of Random Defect Limited Yields”,Proceedings of the 1999 IEEE International Symposium on Semiconductor Manufacturing, (Piscataway, NJ: Institute of Electrical and Electronics Engineers), pp. 403-406. 1999 (no month).
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Caywood John
Lepejian David
Segal Julie
Heuristics Physics Laboratories, Inc.
Sierra Patent Group Ltd.
Thompson A. M.
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