Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-11-29
2003-07-29
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000
Reexamination Certificate
active
06599842
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process and apparatus for etching silicon. More specifically, the present invention relates to trench etching and to forming trench structures in a silicon substrate.
Trench etching is a common procedure in the semiconductor fabrication process. The trenches are etched into a silicon substrate to form structures such as vertical transistors, isolation trenches, capacitors and others found in integrated circuits. Trenches are generally etched by forming a patterned photoresist on the surface of the substrate and then etching the exposed parts of the substrate. One or more layers of material are formed over the trench, as required, depending on the structure desired.
Referring to
FIG. 1
, as explained above, one use of a trench is for the formation of a vertical transistor
50
. The transistor includes a trench
52
, a gate oxide
54
formed over trench
52
, and a polysilicon layer
56
deposited over the gate oxide and filling the trench. A drain region
58
is provided at a portion of substrate
51
adjacent to the top corners of the trench. A source region
60
is provided at a portion of substrate
51
adjacent to the bottom of corners of the trench. A channel
62
is formed between the source and drain regions to electrically couple the two regions when a voltage is applied to polysilicon
56
.
Trench
52
may be formed using either wet etch techniques or dry etch techniques. Currently, dry etch techniques, particularly anisotropic methods, are generally used to form a trench with a high aspect ratio. The aspect ratio refers to a ratio of trench height to trench width. An anisotropic etch technique generally involves accelerating ions toward the substrate to etch the exposed portions of the substrate. The ions are accelerated vertically so the etching is done mostly in a vertical direction. The trench formed using such a method tends to have sharp top and bottom corners
64
and
66
. The electrical field intensity at the corners increases proportionally with the sharpness of the corners. Therefore, sharp corners
64
and
66
lower the breakdown voltage of transistor
50
, i.e., the maximum voltage that can be safely handled by a transistor without oxide breakdown.
In addition, ion bombardment from the anisotropic etching process may damage the outer silicon surface of the trench (e.g., outer 50-100 angstrom). For example, ion bombardment may leave the surfaces of the trench walls with numerous tiny craters, i.e., uneven surfaces. The bombardment also dislodges silicon atoms from the crystal structure and damages the crystal structure, which alters the electrical properties of the silicon substrate.
Therefore, semiconductor manufacturers generally desire to round the corners of a trench and repair the damaged outer surfaces before filling the trench and completing the formation of an integrated circuit. This process conventionally involves using at least two different etching chambers, for example, a capacitance-type etcher, and a microwave downstream etcher. The capacitance-type etcher ignites a plasma within its process chamber and uses ion bombardment to round the top corners. Then the substrate is transferred to a microwave downstream etcher. The microwave downstream etcher ignites a plasma remote from the process chamber. Radicals from the remote plasma are flowed into the process chamber to isotropically etch the trench. This isotropic etch simultaneously rounds the bottom corners and removes the damaged outer surfaces from the trench sidewalls. The top comers are further rounded during this isotropic etching.
While the conventional method works well for some processes, improvements to the process are desirable. First, the conventional process requires the use of two or more different etch chambers to modify the contour of a trench. Also, since the process simultaneously rounds the bottom corners and removes the damaged outer surfaces, these steps cannot be independently controlled. Accordingly, there is a need for an etch method which allows the contour of a trench to be modified in a single chamber and which performs the top corner rounding, bottom corner rounding, and damaged outer surface removal steps separately.
SUMMARY OF THE INVENTION
The present invention provides an improved method for modifying the contour of a trench formed on a substrate. The method rounds the top corners of the trench and performs additional trench contouring in a single chamber. The additional trench contouring includes either or both rounding the bottom corners of the trench and removing damaged outer surfaces of the trench. The method of the present invention performs each of the trench contour modification steps independently in a sequential, in-situ process that allows the contour of a trench to be tailored to a particular process. The present invention is particularly useful for the formation of high-aspect-ratio trenches in a semiconductor fabrication process.
In one embodiment of the present invention, a substrate disposed in a substrate processing chamber is etched to modify the contour of a trench formed on the substrate. The substrate processing chamber is the type that has a coil and a plasma generation system including a source power system operatively coupled to the coil and a bias power system operatively coupled to the substrate process chamber. The substrate is transferred into the substrate process chamber. The substrate is then exposed to a plasma formed from a first process gas consisting essentially of a sputtering agent by applying RF energy from the source power system to the coil. The plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a second process gas without applying bias power or applying minimal bias power to the substrate process chamber.
In another embodiment of the present invention, a substrate disposed in a substrate processing chamber is etched to modify the contour of a trench formed on the substrate. The substrate processing chamber includes a bias power system operatively coupled to the substrate process chamber. The substrate is transferred into the substrate process chamber. A first plasma is ignited from a first process gas consisting essentially of a sputtering agent. The substrate is exposed to ions and electrons dissociated in the first plasma, and the plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, a second plasma is ignited from a second process gas having a halogen source, and the substrate is exposed to ions and radicals dissociated in the second plasma without applying bias power or applying minimal biasing power to the substrate process chamber. The first and second plasmas can be formed remote from the substrate processing chamber or can be formed within the chamber.
Yet in another embodiment of the present invention, a substrate is etched to form a trench thereon. A photoresist layer is patterned on the substrate to define a location for the trench. The substrate is etched to form the trench. The photoresist layer is stripped from the substrate. The substrate is transferred into a substrate processing chamber having a plasma generation system with separate controls that can independently adjust source power and bias power. The substrate is processed by flowing a first gas consisting essentially of a sputtering agent into the chamber to form a first plasma from the first gas and etching the substrate with the first plasma by applying both source power and bias power. Thereafter, a second gas including a halogen source is flowed into the substrate process chamber to form a second plasma from the second gas. The substrate is etched with the second plasma by lowering or grounding the bias power being applied to the chamber.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.
REFERENCE
Chao John
Chinn Jeffrey D.
Jain Mohit
Applied Materials Inc.
Bach Joseph
Kunemund Robert
Townsend & Townsend & Crew
Vinh Lan
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