Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-25
2008-10-07
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S288000, C438S591000, C438S593000, C438S201000, C438S211000, C438S260000, C438S479000, C977S774000, C977S779000, C977S780000, C977S943000, C257SE21423
Reexamination Certificate
active
07432158
ABSTRACT:
A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.
REFERENCES:
patent: 5830538 (1998-11-01), Gates et al.
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6127696 (2000-10-01), Sery et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6320784 (2001-11-01), Muralidhar et al.
patent: 6339002 (2002-01-01), Chan et al.
patent: 6344403 (2002-02-01), Madhukar et al.
patent: 6413819 (2002-07-01), Zafar et al.
patent: 6444545 (2002-09-01), Sadd et al.
patent: 6455372 (2002-09-01), Weimer
patent: 6580132 (2003-06-01), Chan et al.
patent: 6656792 (2003-12-01), Choi et al.
patent: 6713127 (2004-03-01), Subramony et al.
patent: 6784103 (2004-08-01), Rao et al.
patent: 6808986 (2004-10-01), Rao et al.
patent: 6884685 (2005-04-01), Luo et al.
patent: 6903967 (2005-06-01), Mathew et al.
patent: 6946346 (2005-09-01), Chae et al.
patent: 6949455 (2005-09-01), Pham et al.
patent: 6958265 (2005-10-01), Steimle et al.
patent: 6964902 (2005-11-01), Steimle et al.
patent: 6969883 (2005-11-01), Chindalore et al.
patent: 6991987 (2006-01-01), Guo et al.
patent: 7012298 (2006-03-01), Krivokapic
patent: 7015090 (2006-03-01), Okazaki et al.
patent: 2004/0043583 (2004-03-01), Rao et al.
patent: 2004/0104425 (2004-06-01), Kobayashi et al.
patent: 2004/0106285 (2004-06-01), Zacharias
patent: 2004/0130941 (2004-07-01), Kan et al.
patent: 2004/0135204 (2004-07-01), Wang et al.
patent: 2004/0150024 (2004-08-01), Mazoyer et al.
patent: 2004/0212019 (2004-10-01), Shinohara et al.
patent: 2005/0014335 (2005-01-01), Goldbach et al.
patent: 2005/0029572 (2005-02-01), Schmitz
patent: 2005/0037574 (2005-02-01), Sugiyama
patent: 2005/0090062 (2005-04-01), Wang
patent: 2005/0098822 (2005-05-01), Mathew et al.
patent: 2005/0287729 (2005-12-01), Steimle
patent: 2006/0105522 (2006-05-01), Steimle et al.
patent: 2006/0110883 (2006-05-01), Min
patent: 2007/0034142 (2007-02-01), Pescini et al.
patent: 2007/0202708 (2007-08-01), Luo et al.
American Heritage Dictionary, around, from Dictionary.com.
U.S. Appl. No. 11/376,410, filed Mar. 15, 1006.
U.S. Appl. No. 11/376,411, filed Mar. 15, 1006.
U.S. Appl. No. 10/876,820, filed Jun. 25, 2004.
Puglisi et al, “Partial self-ordering observed in silicon nanoclusters deposited on silicon oxide substrate by chemical vapor deposition”,Surface Science, 550 (2004), pp. 1-9.
Leach et al., “Cracking Assisted Nucleation in Chemical Vapor Deposition on Silicon Dioxide,” Journal of Crystal Growth, (2002) vol. 240, No. 3-4, pp. 415-422.
Hu et al., “Real Time Investigation of Nucleation and Growth of Silicon on Silicon Dioxide Using Silane and Disilane in a Rapid Thermal Processing System,” J. Vac. Sci. Technol. B 14(2), Mar./Apr. 1996, pp. 744-750.
De Blauwe et al., “A Novel, Aerosol-Nanocrystal Floating-Gate Device for Non-Volatile Memory Applications,” Electron Devices Meeting 2000, IEDM Technical Digest. International, pp. 683-686.
Kamins, “Polycrystalline Silicon for Integrated Circuits and Displays,” 2nd Edition, Kluwer Academic Publishers, 1998, Boston, p. 44.
Madhukar et al., “CVD Growth of Si Nanocrystals on Dielectric Surfaces for Noncrystal Floating Gate Memory Application,” Materials Research Society Proc. vol. 638, 2001 Materials Research Society, pp. F5.2.1-F5.3.1.
Baron et al., “Growth by Low Pressure Chemical Vapor Deposition of Silicon Quantum Dots on Insulator for Nanoelectronics Devices,” Materials Research Society Sumposium Proc. vol. 571, 2000 Materials Research Society, pp. 37-42.
Qin et al., “Observation of Coulomb-Blockade in a Field-Effect Transistor With Silicon Nanocrystal Floating Gate at Room Temperature,” Solid State Communications 111, 1999, pp. 171-174.
Mazen F. et al., “Control of Silicon Quantum Dots Nucleation and Growth by CVC,” Materials Research Society, Symposium Procedures, vol. 737, pp. F1.9.1-F1.9.6 (2003).
Oishi, Masato et al, “Fabrication of Silicon Nano-Crystal Dots on SiO2 by Ultrahigh-Vacuum Chemical apor Deposition,” Materials Research Society, Symposium Procedures, vol. 638, 3 pgs. (2001).
Ranade et al.; “Work Function Engineering of Molybdenum Gate Electrodes by Nitrogen Implantation”; Electrochemical and Solid-State Letters; G85-G87; 2001.
Zhu, Jane G. et al.; “Effects of Ion Beam Mixing on the Formation of SiGe Nanocrystals by Ion Implantation”; Proceedings of the 11th International Conference on Ion Implantation Technology; Jun. 16-21, 1996; 1 pg abstract & pp. 690-693; IEEE; USA.
Kim, Dong-Won; “Charge retention characteristics of SiGe quantum dot flash memories”; Conference Digest, Device Research Conference; 2002; 1 pg. abstract & pp. 151-152; IEEE; USA.
Cavins et al., “A Nitride-Oxide Blocking Layer for Scaled SONOS Non-Volatile Memory,” Motorola, Inc., Jan. 10, 2002, 5 pages.
Cavins et al., “Integrated Stacked Gate Oxide and Interpoly Oxide,” Motorola, Inc.,, Nov. 1996, pp. 93-94.
Wolf, Ph.D., S.; “Endpoint-Detection in CMP”; Silicon Processing for the VLSI Era; Title pg & pp. 385-387; vol. 4; Deep Submicron Process Technology; Lattice Press, Sunset Beach,CA, no date.
Solomon, P.M. et al.; “Two Gates Are Better Than One”; IEEE Circuits & Devices Magazine; Jan. 2003; pp. 48-62; IEEE.
Blosse, A.; “PVD Aluminum Dual Damascene Interconnection: Yield Comparison between Counterbore and Self Aligned Approaches”; IITC; 1999; pp. 215-218; IEEE.
Lai, “Tunnel Oxide and ETOXTM Flash Scaling Limitation,” IEEE 1998 Int'l Nonvolatile Memory Technology Conference, pp. 6-7.
Huang, Shaoyun et al; “Toward Long-Term Retention-Time Single-Electron-Memory Devices Based on Nitrided Nanocrystalline Silicon Dots”; IEEE Transactions on Nanotechnology; Mar. 2004; pp. 210-214; vol. 3 No. 1; IEEE.
Luo Tien Ying
Muralidhar Ramachandran
Rao Rajesh A.
Steimle Robert F.
Straub Sherry G.
Clingan, Jr. James L.
Estrada Michelle
Freescale Semiconductor Inc.
King Robert L.
Parendo Kevin A
LandOfFree
Method for retaining nanocluster size and electrical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for retaining nanocluster size and electrical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for retaining nanocluster size and electrical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4018313