Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle
Reexamination Certificate
2007-09-06
2011-11-22
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
C716S055000
Reexamination Certificate
active
08065635
ABSTRACT:
A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing.
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Abe Takayuki
Suzuki Junichi
Yashima Jun
Chiang Jack
NuFlare Technology, Inc.
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Sandoval Patrick
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