Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-06-09
2004-08-31
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S718000
Reexamination Certificate
active
06785175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a repair method for a memory cell, and more particular to a method that repairs detected errors after testing.
2. Description of the Related Art
Integrated Circuit (IC) process consists of IC design, wafer manufacturing, wafer testing, and wafer assembly. After design and manufacture, wafers need to be assembled for sale. Since waste of resources can occur when assembling a defective wafer, every chip on a wafer must be tested before being assembled.
FIG. 1
shows a conventional method of checking a wafer with a probe.
In
FIG. 1
, the test machine comprises a probe head
12
, the probe head
12
comprises a body
122
and a testing plate
124
. A probe
126
is electrically connected to the body
122
of the probe head
12
via the testing plate
124
to transmit signals when the probe
126
contacts the bonding pad
162
of the wafer
16
, set on a loading stage
10
, such that the plate
124
can be changed corresponding to different circuits of the wafer
16
.
A microscope
14
is connected to the aperture
128
of the probe head
12
to ensure probe contact with the bonding pad
162
when the probe
126
of the plate
124
aligns with and connects to the bonding pad
162
. The loading stage
10
can be adjusted until the probe
126
contacts the bonding pad
162
to test the wafer
16
.
A conventional semiconductor memory contains not only regular memory unit arrays but also spare memory unit arrays. A spare memory unit array functions as a backup memory unit array by filling in for defective parts of the defective regular memory unit array. Semiconductor memory devices here comprise RAM, DRAM, or SDRAM, and the regular memory unit array comprises bit lines.
FIG. 2
shows a conventional method for substituting a spare memory unit array for a regular memory unit array.
An address of defective line in the regular memory unit array
211
can be set by cutting the fuse unit of the spare decoder
215
.
When a defined address signal is provided to the spare decoder
215
, the decoder
215
can cooperate with the spare switch
213
, so that a specific spare unit line in the spare memory unit array
214
can replace any defective lines on the regular memory unit array
211
.
Test machines can only utilize compression test or normal testing modes, namely non-compression modes, because of the redundancy algorithm.
Most leading semiconductor companies have developed test techniques using compression testing mode for wafer testing to reduce time and costs, but some defects cannot be detected using the compression testing mode, resulting in defective memory devices reaching the assembly stage.
Defects in all memory devices can be detected with a normal testing mode, but this represents increased test time and cost.
SUMMARY OF THE INVENTION
The present invention is directed to a method for repairing a memory cell.
Accordingly, the present invention provides one embodiment of the method for repairing a memory cell, wherein the memory cell has a plurality of bit lines. A memory cell is provided, and the memory cell is tested with a compression testing mode. Future testing is set to compression testing mode when an error is detected, or, when no error is detected, as normal testing mode, after which the thus-far error-free cell is tested again, this time with a normal testing mode. It is determined whether detected errors warrant repair, and all repairs deemed necessary are then performed.
Accordingly, the present invention also provides another method for repairing a memory cell. A memory cell is provided, wherein the memory cell has a plurality of regular bit lines. The regular bit lines are separated into groups of N strips. Each group of regular bit lines is tested with a compression testing mode. Future tests are set to compression testing mode when errors are detected, or, when no errors are detected, to a normal testing mode. Detected errors are recorded for future reference. Groups of regular bit lines on which no error has yet been detected are then tested again, this time with normal testing mode. Detected errors are recorded for future reference. It is determined whether detected errors warrant repair, and all repairs deemed necessary are performed.
REFERENCES:
patent: 6085334 (2000-07-01), Giles et al.
patent: 6119251 (2000-09-01), Cloud et al.
patent: 6304251 (2001-10-01), Ito et al.
patent: 6581172 (2003-06-01), Totorica et al.
Chang Chin-Min
Shen Yu-Lin
Wu Cheng-Cheng
Dinh Son T.
Ladas & Parry
Nanya Technology Corporation
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